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Re: [Qemu-devel] [PATCH v1 11/30] RISC-V: Split out mstatus_fs from tb_f
From: |
Philippe Mathieu-Daudé |
Subject: |
Re: [Qemu-devel] [PATCH v1 11/30] RISC-V: Split out mstatus_fs from tb_flags |
Date: |
Wed, 23 May 2018 09:25:17 -0300 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 |
On 05/22/2018 09:14 PM, Michael Clark wrote:
> From: Richard Henderson <address@hidden>
>
> Cc: Sagar Karandikar <address@hidden>
> Cc: Bastian Koppelmann <address@hidden>
> Cc: Palmer Dabbelt <address@hidden>
> Cc: Alistair Francis <address@hidden>
> Cc: Richard Henderson <address@hidden>
> Signed-off-by: Michael Clark <address@hidden>
> Reviewed-by: Michael Clark <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
> ---
> target/riscv/cpu.h | 6 +++---
> target/riscv/translate.c | 10 +++++-----
> 2 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 3a3d91447736..242a8fcbe180 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -276,8 +276,8 @@ void QEMU_NORETURN do_raise_exception_err(CPURISCVState
> *env,
> target_ulong cpu_riscv_get_fflags(CPURISCVState *env);
> void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong);
>
> -#define TB_FLAGS_MMU_MASK 3
> -#define TB_FLAGS_FP_ENABLE MSTATUS_FS
> +#define TB_FLAGS_MMU_MASK 3
> +#define TB_FLAGS_MSTATUS_FS MSTATUS_FS
>
> static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
> target_ulong *cs_base, uint32_t
> *flags)
> @@ -285,7 +285,7 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState
> *env, target_ulong *pc,
> *pc = env->pc;
> *cs_base = 0;
> #ifdef CONFIG_USER_ONLY
> - *flags = TB_FLAGS_FP_ENABLE;
> + *flags = TB_FLAGS_MSTATUS_FS;
> #else
> *flags = cpu_mmu_index(env, 0) | (env->mstatus & MSTATUS_FS);
> #endif
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index ee2bbc55b051..466b9551cbd9 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -44,7 +44,7 @@ typedef struct DisasContext {
> /* pc_succ_insn points to the instruction following base.pc_next */
> target_ulong pc_succ_insn;
> uint32_t opcode;
> - uint32_t flags;
> + uint32_t mstatus_fs;
> uint32_t mem_idx;
> /* Remember the rounding mode encoded in the previous fp instruction,
> which we have already installed into env->fp_status. Or -1 for
> @@ -656,7 +656,7 @@ static void gen_fp_load(DisasContext *ctx, uint32_t opc,
> int rd,
> {
> TCGv t0;
>
> - if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) {
> + if (ctx->mstatus_fs == 0) {
> gen_exception_illegal(ctx);
> return;
> }
> @@ -686,7 +686,7 @@ static void gen_fp_store(DisasContext *ctx, uint32_t opc,
> int rs1,
> {
> TCGv t0;
>
> - if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) {
> + if (ctx->mstatus_fs == 0) {
> gen_exception_illegal(ctx);
> return;
> }
> @@ -945,7 +945,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc,
> int rd,
> {
> TCGv t0 = NULL;
>
> - if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) {
> + if (ctx->mstatus_fs == 0) {
> goto do_illegal;
> }
>
> @@ -1810,8 +1810,8 @@ static void
> riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
> DisasContext *ctx = container_of(dcbase, DisasContext, base);
>
> ctx->pc_succ_insn = ctx->base.pc_first;
> - ctx->flags = ctx->base.tb->flags;
> ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK;
> + ctx->mstatus_fs = ctx->base.tb->flags & TB_FLAGS_MSTATUS_FS;
> ctx->frm = -1; /* unknown rounding mode */
> }
>
>
- Re: [Qemu-devel] [PATCH v1 05/30] RISC-V: Allow setting and clearing multiple irqs, (continued)
- [Qemu-devel] [PATCH v1 06/30] RISC-V: Move non-ops from op_helper to cpu_helper, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 07/30] RISC-V: Update CSR and interrupt definitions, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 09/30] RISC-V: Implement atomic mip/sip CSR updates, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 10/30] RISC-V: Implement existential predicates for CSRs, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 08/30] RISC-V: Implement modular CSR helper interface, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 11/30] RISC-V: Split out mstatus_fs from tb_flags, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 12/30] RISC-V: Mark mstatus.fs dirty, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 13/30] RISC-V: Implement mstatus.TSR/TW/TVM, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 14/30] RISC-V: Add public API for the CSR dispatch table, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 15/30] RISC-V: Add hartid and \n to interrupt logging, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 16/30] RISC-V: Use riscv prefix consistently on cpu helpers, Michael Clark, 2018/05/22