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[Qemu-devel] [PULL 08/28] hw/arm/virt: GICv3 DT node with one or two red
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 08/28] hw/arm/virt: GICv3 DT node with one or two redistributor regions |
Date: |
Fri, 22 Jun 2018 13:56:53 +0100 |
From: Eric Auger <address@hidden>
This patch allows the creation of a GICv3 node with 1 or 2
redistributor regions depending on the number of smu_cpus.
The second redistributor region is located just after the
existing RAM region, at 256GB and contains up to up to 512 vcpus.
Please refer to kernel documentation for further node details:
Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt
Signed-off-by: Eric Auger <address@hidden>
Reviewed-by: Andrew Jones <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
include/hw/arm/virt.h | 14 ++++++++++++++
hw/arm/virt.c | 29 ++++++++++++++++++++++++-----
2 files changed, 38 insertions(+), 5 deletions(-)
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index 4ac7ef6a374..308156f0cdf 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -35,6 +35,8 @@
#include "qemu/notify.h"
#include "hw/boards.h"
#include "hw/arm/arm.h"
+#include "sysemu/kvm.h"
+#include "hw/intc/arm_gicv3_common.h"
#define NUM_GICV2M_SPIS 64
#define NUM_VIRTIO_TRANSPORTS 32
@@ -60,6 +62,7 @@ enum {
VIRT_GIC_V2M,
VIRT_GIC_ITS,
VIRT_GIC_REDIST,
+ VIRT_GIC_REDIST2,
VIRT_SMMU,
VIRT_UART,
VIRT_MMIO,
@@ -130,4 +133,15 @@ typedef struct {
void virt_acpi_setup(VirtMachineState *vms);
+/* Return the number of used redistributor regions */
+static inline int virt_gicv3_redist_region_count(VirtMachineState *vms)
+{
+ uint32_t redist0_capacity =
+ vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
+
+ assert(vms->gic_version == 3);
+
+ return vms->smp_cpus > redist0_capacity ? 2 : 1;
+}
+
#endif /* QEMU_ARM_VIRT_H */
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index de189c72960..e5e7606946f 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -149,6 +149,8 @@ static const MemMapEntry a15memmap[] = {
[VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 },
[VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 },
[VIRT_MEM] = { 0x40000000, RAMLIMIT_BYTES },
+ /* Additional 64 MB redist region (can contain up to 512 redistributors) */
+ [VIRT_GIC_REDIST2] = { 0x4000000000ULL, 0x4000000 },
/* Second PCIe window, 512GB wide at the 512GB boundary */
[VIRT_PCIE_MMIO_HIGH] = { 0x8000000000ULL, 0x8000000000ULL },
};
@@ -402,13 +404,30 @@ static void fdt_add_gic_node(VirtMachineState *vms)
qemu_fdt_setprop_cell(vms->fdt, "/intc", "#size-cells", 0x2);
qemu_fdt_setprop(vms->fdt, "/intc", "ranges", NULL, 0);
if (vms->gic_version == 3) {
+ int nb_redist_regions = virt_gicv3_redist_region_count(vms);
+
qemu_fdt_setprop_string(vms->fdt, "/intc", "compatible",
"arm,gic-v3");
- qemu_fdt_setprop_sized_cells(vms->fdt, "/intc", "reg",
- 2, vms->memmap[VIRT_GIC_DIST].base,
- 2, vms->memmap[VIRT_GIC_DIST].size,
- 2, vms->memmap[VIRT_GIC_REDIST].base,
- 2, vms->memmap[VIRT_GIC_REDIST].size);
+
+ qemu_fdt_setprop_cell(vms->fdt, "/intc",
+ "#redistributor-regions", nb_redist_regions);
+
+ if (nb_redist_regions == 1) {
+ qemu_fdt_setprop_sized_cells(vms->fdt, "/intc", "reg",
+ 2, vms->memmap[VIRT_GIC_DIST].base,
+ 2, vms->memmap[VIRT_GIC_DIST].size,
+ 2, vms->memmap[VIRT_GIC_REDIST].base,
+ 2, vms->memmap[VIRT_GIC_REDIST].size);
+ } else {
+ qemu_fdt_setprop_sized_cells(vms->fdt, "/intc", "reg",
+ 2, vms->memmap[VIRT_GIC_DIST].base,
+ 2, vms->memmap[VIRT_GIC_DIST].size,
+ 2, vms->memmap[VIRT_GIC_REDIST].base,
+ 2, vms->memmap[VIRT_GIC_REDIST].size,
+ 2, vms->memmap[VIRT_GIC_REDIST2].base,
+ 2,
vms->memmap[VIRT_GIC_REDIST2].size);
+ }
+
if (vms->virt) {
qemu_fdt_setprop_cells(vms->fdt, "/intc", "interrupts",
GIC_FDT_IRQ_TYPE_PPI, ARCH_GICV3_MAINT_IRQ,
--
2.17.1
- [Qemu-devel] [PULL 00/28] target-arm queue, Peter Maydell, 2018/06/22
- [Qemu-devel] [PULL 10/28] hw/arm/virt: Register two redistributor regions when necessary, Peter Maydell, 2018/06/22
- [Qemu-devel] [PULL 12/28] hw/arm/virt: Add virt-3.0 machine type, Peter Maydell, 2018/06/22
- [Qemu-devel] [PULL 11/28] hw/arm/virt: Add a new 256MB ECAM region, Peter Maydell, 2018/06/22
- [Qemu-devel] [PULL 13/28] hw/arm/virt: Use 256MB ECAM region by default, Peter Maydell, 2018/06/22
- [Qemu-devel] [PULL 09/28] hw/arm/virt-acpi-build: Advertise one or two GICR structures, Peter Maydell, 2018/06/22
- [Qemu-devel] [PULL 08/28] hw/arm/virt: GICv3 DT node with one or two redistributor regions,
Peter Maydell <=
- [Qemu-devel] [PULL 07/28] hw/intc/arm_gicv3_kvm: Get prepared to handle multiple redist regions, Peter Maydell, 2018/06/22
- [Qemu-devel] [PULL 14/28] hw/arm/virt: Increase max_cpus to 512, Peter Maydell, 2018/06/22
- [Qemu-devel] [PULL 04/28] linux-headers: Update to kernel mainline commit b357bf602, Peter Maydell, 2018/06/22
- [Qemu-devel] [PULL 05/28] target/arm: Allow KVM device address overwriting, Peter Maydell, 2018/06/22
- [Qemu-devel] [PULL 18/28] hw/misc/tz-mpc.c: Implement registers, Peter Maydell, 2018/06/22
- [Qemu-devel] [PULL 20/28] hw/misc/tz_mpc.c: Honour the BLK_LUT settings in translate, Peter Maydell, 2018/06/22
- [Qemu-devel] [PULL 25/28] target/arm: Introduce ARM_FEATURE_M_MAIN, Peter Maydell, 2018/06/22
- [Qemu-devel] [PULL 15/28] target-arm: Add the Cortex-R5F, Peter Maydell, 2018/06/22
- [Qemu-devel] [PULL 16/28] xlnx-zynqmp: Swap Cortex-R5 for Cortex-R5F, Peter Maydell, 2018/06/22
- [Qemu-devel] [PULL 03/28] target-arm: fix a segmentation fault due to illegal memory access, Peter Maydell, 2018/06/22