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[Qemu-devel] [PULL 18/25] target/openrisc: Stub out handle_mmu_fault for
From: |
Stafford Horne |
Subject: |
[Qemu-devel] [PULL 18/25] target/openrisc: Stub out handle_mmu_fault for softmmu |
Date: |
Mon, 2 Jul 2018 22:57:59 +0900 |
From: Richard Henderson <address@hidden>
This hook is only used by CONFIG_USER_ONLY.
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Stafford Horne <address@hidden>
---
target/openrisc/mmu.c | 35 +++++------------------------------
1 file changed, 5 insertions(+), 30 deletions(-)
diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c
index a4613e9ae4..f4c0a3e217 100644
--- a/target/openrisc/mmu.c
+++ b/target/openrisc/mmu.c
@@ -177,42 +177,17 @@ static void cpu_openrisc_raise_mmu_exception(OpenRISCCPU
*cpu,
cpu->env.lock_addr = -1;
}
-#ifndef CONFIG_USER_ONLY
int openrisc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size,
int rw, int mmu_idx)
{
+#ifdef CONFIG_USER_ONLY
OpenRISCCPU *cpu = OPENRISC_CPU(cs);
- int ret = 0;
- hwaddr physical = 0;
- int prot = 0;
-
- ret = get_phys_addr(cpu, &physical, &prot, address, rw);
-
- if (ret == TLBRET_MATCH) {
- tlb_set_page(cs, address & TARGET_PAGE_MASK,
- physical & TARGET_PAGE_MASK, prot,
- mmu_idx, TARGET_PAGE_SIZE);
- ret = 0;
- } else if (ret < 0) {
- cpu_openrisc_raise_mmu_exception(cpu, address, rw, ret);
- ret = 1;
- }
-
- return ret;
-}
+ cpu_openrisc_raise_mmu_exception(cpu, address, rw, 0);
+ return 1;
#else
-int openrisc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size,
- int rw, int mmu_idx)
-{
- OpenRISCCPU *cpu = OPENRISC_CPU(cs);
- int ret = 0;
-
- cpu_openrisc_raise_mmu_exception(cpu, address, rw, ret);
- ret = 1;
-
- return ret;
-}
+ g_assert_not_reached();
#endif
+}
#ifndef CONFIG_USER_ONLY
hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
--
2.17.0
- [Qemu-devel] [PULL 07/25] target/openrisc: Link more translation blocks, (continued)
- [Qemu-devel] [PULL 07/25] target/openrisc: Link more translation blocks, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 09/25] target/openrisc: Exit the TB after l.mtspr, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 10/25] target/openrisc: Form the spr index from tcg, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 11/25] target/openrisc: Merge tlb allocation into CPUOpenRISCState, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 12/25] target/openrisc: Remove indirect function calls for mmu, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 13/25] target/openrisc: Merge mmu_helper.c into mmu.c, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 14/25] target/openrisc: Reduce tlb to a single dimension, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 15/25] target/openrisc: Fix tlb flushing in mtspr, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 16/25] target/openrisc: Fix cpu_mmu_index, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 17/25] target/openrisc: Use identical sizes for ITLB and DTLB, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 18/25] target/openrisc: Stub out handle_mmu_fault for softmmu,
Stafford Horne <=
- [Qemu-devel] [PULL 19/25] target/openrisc: Increase the TLB size, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 20/25] target/openrisc: Reorg tlb lookup, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 21/25] target/openrisc: Add support in scripts/qemu-binfmt-conf.sh, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 23/25] linux-user: Fix struct sigaltstack for openrisc, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 22/25] linux-user: Implement signals for openrisc, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 24/25] target/openrisc: Fix delay slot exception flag to match spec, Stafford Horne, 2018/07/02
- [Qemu-devel] [PULL 25/25] target/openrisc: Fix writes to interrupt mask register, Stafford Horne, 2018/07/02
- Re: [Qemu-devel] [PULL 00/25] OpenRISC updates for 3.0, Stafford Horne, 2018/07/02
- Re: [Qemu-devel] [PULL 00/25] OpenRISC updates for 3.0, Alex Bennée, 2018/07/02