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[Qemu-devel] [PULL v4 22/46] target/mips: Implement emulation of nanoMIP
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL v4 22/46] target/mips: Implement emulation of nanoMIPS EXTW instruction |
Date: |
Thu, 23 Aug 2018 15:34:12 +0200 |
From: James Hogan <address@hidden>
Implement emulation of nanoMIPS EXTW instruction. EXTW instruction
is similar to the MIPS r6 ALIGN instruction, except that it counts
the other way and in bits instead of bytes. We therefore generalise
gen_align() function into a new gen_align_bits() function (which
counts in bits instead of bytes and optimises when bits = size of
the word), and implement gen_align() and a new gen_ext() based on
that. Since we need to know the word size to check for when the
number of bits == the word size, the opc argument is replaced with
a wordsz argument (either 32 or 64).
Signed-off-by: James Hogan <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Stefan Markovic <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target/mips/translate.c | 53 +++++++++++++++++++++++++++++++++----------------
1 file changed, 36 insertions(+), 17 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 5da5dcd..4fc94c6 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -4870,8 +4870,8 @@ static void gen_lsa(DisasContext *ctx, int opc, int rd,
int rs, int rt,
return;
}
-static void gen_align(DisasContext *ctx, int opc, int rd, int rs, int rt,
- int bp)
+static void gen_align_bits(DisasContext *ctx, int wordsz, int rd, int rs,
+ int rt, int bits)
{
TCGv t0;
if (rd == 0) {
@@ -4879,35 +4879,40 @@ static void gen_align(DisasContext *ctx, int opc, int
rd, int rs, int rt,
return;
}
t0 = tcg_temp_new();
- gen_load_gpr(t0, rt);
- if (bp == 0) {
- switch (opc) {
- case OPC_ALIGN:
+ if (bits == 0 || bits == wordsz) {
+ if (bits == 0) {
+ gen_load_gpr(t0, rt);
+ } else {
+ gen_load_gpr(t0, rs);
+ }
+ switch (wordsz) {
+ case 32:
tcg_gen_ext32s_tl(cpu_gpr[rd], t0);
break;
#if defined(TARGET_MIPS64)
- case OPC_DALIGN:
+ case 64:
tcg_gen_mov_tl(cpu_gpr[rd], t0);
break;
#endif
}
} else {
TCGv t1 = tcg_temp_new();
+ gen_load_gpr(t0, rt);
gen_load_gpr(t1, rs);
- switch (opc) {
- case OPC_ALIGN:
+ switch (wordsz) {
+ case 32:
{
TCGv_i64 t2 = tcg_temp_new_i64();
tcg_gen_concat_tl_i64(t2, t1, t0);
- tcg_gen_shri_i64(t2, t2, 8 * (4 - bp));
+ tcg_gen_shri_i64(t2, t2, 32 - bits);
gen_move_low32(cpu_gpr[rd], t2);
tcg_temp_free_i64(t2);
}
break;
#if defined(TARGET_MIPS64)
- case OPC_DALIGN:
- tcg_gen_shli_tl(t0, t0, 8 * bp);
- tcg_gen_shri_tl(t1, t1, 8 * (8 - bp));
+ case 64:
+ tcg_gen_shli_tl(t0, t0, bits);
+ tcg_gen_shri_tl(t1, t1, 64 - bits);
tcg_gen_or_tl(cpu_gpr[rd], t1, t0);
break;
#endif
@@ -4918,6 +4923,18 @@ static void gen_align(DisasContext *ctx, int opc, int
rd, int rs, int rt,
tcg_temp_free(t0);
}
+static void gen_align(DisasContext *ctx, int wordsz, int rd, int rs, int rt,
+ int bp)
+{
+ gen_align_bits(ctx, wordsz, rd, rs, rt, bp * 8);
+}
+
+static void gen_ext(DisasContext *ctx, int wordsz, int rd, int rs, int rt,
+ int shift)
+{
+ gen_align_bits(ctx, wordsz, rd, rs, rt, wordsz - shift);
+}
+
static void gen_bitswap(DisasContext *ctx, int opc, int rd, int rt)
{
TCGv t0;
@@ -14410,8 +14427,7 @@ static void decode_micromips32_opc(CPUMIPSState *env,
DisasContext *ctx)
break;
case ALIGN:
check_insn(ctx, ISA_MIPS32R6);
- gen_align(ctx, OPC_ALIGN, rd, rs, rt,
- extract32(ctx->opcode, 9, 2));
+ gen_align(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 9, 2));
break;
case EXT:
gen_bitops(ctx, OPC_EXT, rt, rs, rr, rd);
@@ -17618,6 +17634,9 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env,
DisasContext *ctx)
gen_lsa(ctx, OPC_LSA, rd, rs, rt,
extract32(ctx->opcode, 9, 2) - 1);
break;
+ case NM_EXTW:
+ gen_ext(ctx, 32, rd, rs, rt, extract32(ctx->opcode, 6, 5));
+ break;
case NM_POOL32AXF:
gen_pool32axf_nanomips_insn(env, ctx);
break;
@@ -20465,7 +20484,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env,
DisasContext *ctx)
switch (op2) {
case OPC_ALIGN:
case OPC_ALIGN_END:
- gen_align(ctx, OPC_ALIGN, rd, rs, rt, sa & 3);
+ gen_align(ctx, 32, rd, rs, rt, sa & 3);
break;
case OPC_BITSWAP:
gen_bitswap(ctx, op2, rd, rt);
@@ -20491,7 +20510,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env,
DisasContext *ctx)
switch (op2) {
case OPC_DALIGN:
case OPC_DALIGN_END:
- gen_align(ctx, OPC_DALIGN, rd, rs, rt, sa & 7);
+ gen_align(ctx, 64, rd, rs, rt, sa & 7);
break;
case OPC_DBITSWAP:
gen_bitswap(ctx, op2, rd, rt);
--
2.7.4
- [Qemu-devel] [PULL v4 33/46] target/mips: Add emulation of DSP ASE for nanoMIPS - part 5, (continued)
- [Qemu-devel] [PULL v4 33/46] target/mips: Add emulation of DSP ASE for nanoMIPS - part 5, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 41/46] elf: On elf loading, treat both EM_MIPS and EM_NANOMIPS as legal for MIPS, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 38/46] target/mips: Fix ERET/ERETNC behavior related to ADEL exception, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 42/46] elf: Don't check FCR31_NAN2008 bit for nanoMIPS, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 45/46] mips_malta: Fix semihosting argument passing for nanoMIPS bare metal, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 46/46] target/mips: Add definition of nanoMIPS I7200 CPU, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 43/46] mips_malta: Add basic nanoMIPS boot code for Malta board, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 26/46] target/mips: Add emulation of nanoMIPS 32-bit branch instructions, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 29/46] target/mips: Add emulation of DSP ASE for nanoMIPS - part 1, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 34/46] target/mips: Add emulation of DSP ASE for nanoMIPS - part 6, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 22/46] target/mips: Implement emulation of nanoMIPS EXTW instruction,
Aleksandar Markovic <=
- [Qemu-devel] [PULL v4 25/46] target/mips: Implement emulation of nanoMIPS LLWP/SCWP pair, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 24/46] target/mips: Add CP0 Config3 and Config5 fields to DisasContext structure, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 30/46] target/mips: Add emulation of DSP ASE for nanoMIPS - part 2, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 37/46] target/mips: Add updating BadInstr and BadInstrX for nanoMIPS, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 40/46] elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS too, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 31/46] target/mips: Add emulation of DSP ASE for nanoMIPS - part 3, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 11/46] target/mips: Add emulation of nanoMIPS 16-bit load and store instructions, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 16/46] target/mips: Add emulation of nanoMIPS 48-bit instructions, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 21/46] target/mips: Implement emulation of nanoMIPS ROTX instruction, Aleksandar Markovic, 2018/08/23
- [Qemu-devel] [PULL v4 28/46] target/mips: Implement MT ASE support for nanoMIPS, Aleksandar Markovic, 2018/08/23