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[Qemu-devel] [PULL 03/52] target/arm: Use the int-to-float-scale softflo
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 03/52] target/arm: Use the int-to-float-scale softfloat routines |
Date: |
Fri, 24 Aug 2018 10:32:54 +0100 |
From: Richard Henderson <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/helper.c | 29 +++++------------------------
1 file changed, 5 insertions(+), 24 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index c9bce1efcb2..456bb9cc113 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -11564,12 +11564,7 @@ float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState
*env)
#define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
void *fpstp) \
-{ \
- float_status *fpst = fpstp; \
- float##fsz tmp; \
- tmp = itype##_to_##float##fsz(x, fpst); \
- return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
-}
+{ return itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); }
/* Notice that we want only input-denormal exception flags from the
* scalbn operation: the other possible flags (overflow+inexact if
@@ -11622,38 +11617,24 @@ VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
#undef VFP_CONV_FLOAT_FIX_ROUND
#undef VFP_CONV_FIX_A64
-/* Conversion to/from f16 can overflow to infinity before/after scaling.
- * Therefore we convert to f64, scale, and then convert f64 to f16; or
- * vice versa for conversion to integer.
- *
- * For 16- and 32-bit integers, the conversion to f64 never rounds.
- * For 64-bit integers, any integer that would cause rounding will also
- * overflow to f16 infinity, so there is no double rounding problem.
- */
-
-static float16 do_postscale_fp16(float64 f, int shift, float_status *fpst)
-{
- return float64_to_float16(float64_scalbn(f, -shift, fpst), true, fpst);
-}
-
uint32_t HELPER(vfp_sltoh)(uint32_t x, uint32_t shift, void *fpst)
{
- return do_postscale_fp16(int32_to_float64(x, fpst), shift, fpst);
+ return int32_to_float16_scalbn(x, -shift, fpst);
}
uint32_t HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
{
- return do_postscale_fp16(uint32_to_float64(x, fpst), shift, fpst);
+ return uint32_to_float16_scalbn(x, -shift, fpst);
}
uint32_t HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
{
- return do_postscale_fp16(int64_to_float64(x, fpst), shift, fpst);
+ return int64_to_float16_scalbn(x, -shift, fpst);
}
uint32_t HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
{
- return do_postscale_fp16(uint64_to_float64(x, fpst), shift, fpst);
+ return uint64_to_float16_scalbn(x, -shift, fpst);
}
static float64 do_prescale_fp16(float16 f, int shift, float_status *fpst)
--
2.18.0
- [Qemu-devel] [PULL 00/52] target-arm queue, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 04/52] target/arm: Use the float-to-int-scale softfloat routines, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 07/52] hw/arm/highbank: Connect VIRQ and VFIQ, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 02/52] softfloat: Add scaling float-to-int routines, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 06/52] hw/arm/vexpress: Connect VIRQ and VFIQ, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 05/52] hw/intc/arm_gic: Make per-cpu GICH memory regions 0x200 bytes large, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 03/52] target/arm: Use the int-to-float-scale softfloat routines,
Peter Maydell <=
- [Qemu-devel] [PULL 01/52] softfloat: Add scaling int-to-float routines, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 08/52] hw/arm/fsl-imx6ul: Connect VIRQ and VFIQ, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 11/52] hw/arm/vexpress: Don't set info->secure_boot if CPU doesn't have EL3, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 09/52] hw/arm/fsl-imx6ul: Connect VIRQ and VFIQ, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 12/52] hw/arm/vexpress: Add "virtualization" property controlling presence of EL2, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 13/52] target/arm: Implement RAZ/WI HACTLR2, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 15/52] target/arm: Factor out code for taking an AArch32 exception, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 10/52] hw/cpu/a15mpcore: If CPU has EL2, enable it on the GIC and wire it up, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 16/52] target/arm: Implement support for taking exceptions to Hyp mode, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 18/52] hw/arm/boot: AArch32 kernels should be started in Hyp mode if available, Peter Maydell, 2018/08/24