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[Qemu-devel] [PULL 15/52] target/arm: Factor out code for taking an AArc
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 15/52] target/arm: Factor out code for taking an AArch32 exception |
Date: |
Fri, 24 Aug 2018 10:33:06 +0100 |
Factor out the code which changes the CPU state so as to
actually take an exception to AArch32. We're going to want
to use this for handling exception entry to Hyp mode.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Reviewed-by: Luc Michel <address@hidden>
Message-id: address@hidden
---
target/arm/helper.c | 64 +++++++++++++++++++++++++++++----------------
1 file changed, 41 insertions(+), 23 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 0d5f6f48cfe..b47657c31b2 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8033,6 +8033,46 @@ void aarch64_sync_64_to_32(CPUARMState *env)
env->regs[15] = env->pc;
}
+static void take_aarch32_exception(CPUARMState *env, int new_mode,
+ uint32_t mask, uint32_t offset,
+ uint32_t newpc)
+{
+ /* Change the CPU state so as to actually take the exception. */
+ switch_mode(env, new_mode);
+ /*
+ * For exceptions taken to AArch32 we must clear the SS bit in both
+ * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it
now.
+ */
+ env->uncached_cpsr &= ~PSTATE_SS;
+ env->spsr = cpsr_read(env);
+ /* Clear IT bits. */
+ env->condexec_bits = 0;
+ /* Switch to the new mode, and to the correct instruction set. */
+ env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
+ /* Set new mode endianness */
+ env->uncached_cpsr &= ~CPSR_E;
+ if (env->cp15.sctlr_el[arm_current_el(env)] & SCTLR_EE) {
+ env->uncached_cpsr |= CPSR_E;
+ }
+ env->daif |= mask;
+
+ if (new_mode == ARM_CPU_MODE_HYP) {
+ env->thumb = (env->cp15.sctlr_el[2] & SCTLR_TE) != 0;
+ env->elr_el[2] = env->regs[15];
+ } else {
+ /*
+ * this is a lie, as there was no c1_sys on V4T/V5, but who cares
+ * and we should just guard the thumb mode on V4
+ */
+ if (arm_feature(env, ARM_FEATURE_V4T)) {
+ env->thumb =
+ (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0;
+ }
+ env->regs[14] = env->regs[15] + offset;
+ }
+ env->regs[15] = newpc;
+}
+
static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
{
ARMCPU *cpu = ARM_CPU(cs);
@@ -8175,29 +8215,7 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
env->cp15.scr_el3 &= ~SCR_NS;
}
- switch_mode (env, new_mode);
- /* For exceptions taken to AArch32 we must clear the SS bit in both
- * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it
now.
- */
- env->uncached_cpsr &= ~PSTATE_SS;
- env->spsr = cpsr_read(env);
- /* Clear IT bits. */
- env->condexec_bits = 0;
- /* Switch to the new mode, and to the correct instruction set. */
- env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
- /* Set new mode endianness */
- env->uncached_cpsr &= ~CPSR_E;
- if (env->cp15.sctlr_el[arm_current_el(env)] & SCTLR_EE) {
- env->uncached_cpsr |= CPSR_E;
- }
- env->daif |= mask;
- /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
- * and we should just guard the thumb mode on V4 */
- if (arm_feature(env, ARM_FEATURE_V4T)) {
- env->thumb = (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0;
- }
- env->regs[14] = env->regs[15] + offset;
- env->regs[15] = addr;
+ take_aarch32_exception(env, new_mode, mask, offset, addr);
}
/* Handle exception entry to a target EL which is using AArch64 */
--
2.18.0
- [Qemu-devel] [PULL 02/52] softfloat: Add scaling float-to-int routines, (continued)
- [Qemu-devel] [PULL 02/52] softfloat: Add scaling float-to-int routines, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 06/52] hw/arm/vexpress: Connect VIRQ and VFIQ, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 05/52] hw/intc/arm_gic: Make per-cpu GICH memory regions 0x200 bytes large, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 03/52] target/arm: Use the int-to-float-scale softfloat routines, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 01/52] softfloat: Add scaling int-to-float routines, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 08/52] hw/arm/fsl-imx6ul: Connect VIRQ and VFIQ, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 11/52] hw/arm/vexpress: Don't set info->secure_boot if CPU doesn't have EL3, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 09/52] hw/arm/fsl-imx6ul: Connect VIRQ and VFIQ, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 12/52] hw/arm/vexpress: Add "virtualization" property controlling presence of EL2, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 13/52] target/arm: Implement RAZ/WI HACTLR2, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 15/52] target/arm: Factor out code for taking an AArch32 exception,
Peter Maydell <=
- [Qemu-devel] [PULL 10/52] hw/cpu/a15mpcore: If CPU has EL2, enable it on the GIC and wire it up, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 16/52] target/arm: Implement support for taking exceptions to Hyp mode, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 18/52] hw/arm/boot: AArch32 kernels should be started in Hyp mode if available, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 19/52] hw/misc/mps2-fpgaio: Implement 1Hz and 100Hz counters, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 14/52] target/arm: Implement AArch32 HCR and HCR2, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 17/52] target/arm: Clear CPSR.IL and CPSR.J on 32-bit exception entry, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 20/52] hw/misc/mps2-fpgaio: Implement PSCNTR and COUNTER, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 21/52] hw/timer/cmsdk-apb-dualtimer: Implement CMSDK dual timer module, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 22/52] hw/arm/iotkit: Wire up the dualtimer, Peter Maydell, 2018/08/24
- [Qemu-devel] [PULL 23/52] hw/arm/mps2: Wire up dual-timer in mps2-an385 and mps2-an511, Peter Maydell, 2018/08/24