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[Qemu-devel] [PATCH v4 5/8] target/mips: R5900 DMULT[U], DDIV[U], LL, SC
From: |
Fredrik Noring |
Subject: |
[Qemu-devel] [PATCH v4 5/8] target/mips: R5900 DMULT[U], DDIV[U], LL, SC, LLD and SCD are user only |
Date: |
Sun, 16 Sep 2018 17:13:03 +0200 |
These MIPS III instructions are unavailable and therefore trapped and
emulated by the Linux kernel.
Signed-off-by: Fredrik Noring <address@hidden>
---
target/mips/translate.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 77d678353e..327e96307b 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -22458,6 +22458,7 @@ static void decode_opc_special_legacy(CPUMIPSState
*env, DisasContext *ctx)
case OPC_DMULTU:
case OPC_DDIV:
case OPC_DDIVU:
+ check_insn_opc_user_only(ctx, INSN_R5900);
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
gen_muldiv(ctx, op1, 0, rs, rt);
@@ -24962,6 +24963,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext
*ctx)
break;
case OPC_LL: /* Load and stores */
check_insn(ctx, ISA_MIPS2);
+ check_insn_opc_user_only(ctx, INSN_R5900);
/* Fallthrough */
case OPC_LWL:
case OPC_LWR:
@@ -24987,6 +24989,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext
*ctx)
case OPC_SC:
check_insn(ctx, ISA_MIPS2);
check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_user_only(ctx, INSN_R5900);
gen_st_cond(ctx, op, rt, rs, imm);
break;
case OPC_CACHE:
@@ -25253,9 +25256,11 @@ static void decode_opc(CPUMIPSState *env, DisasContext
*ctx)
#if defined(TARGET_MIPS64)
/* MIPS64 opcodes */
+ case OPC_LLD:
+ check_insn_opc_user_only(ctx, INSN_R5900);
+ /* fall through */
case OPC_LDL:
case OPC_LDR:
- case OPC_LLD:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
/* fall through */
case OPC_LWU:
@@ -25275,6 +25280,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext
*ctx)
break;
case OPC_SCD:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
+ check_insn_opc_user_only(ctx, INSN_R5900);
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
gen_st_cond(ctx, op, rt, rs, imm);
--
2.16.4
- [Qemu-devel] [PATCH v4 0/8] target/mips: Support R5900 GCC programs in user mode, Fredrik Noring, 2018/09/16
- [Qemu-devel] [PATCH v4 1/8] target/mips: Define R5900 instructions and CPU preprocessor constants, Fredrik Noring, 2018/09/16
- [Qemu-devel] [PATCH v4 2/8] target/mips: Support R5900 specific three-operand MULT and MULTU, Fredrik Noring, 2018/09/16
- [Qemu-devel] [PATCH v4 3/8] target/mips: Support R5900 instructions MOVN, MOVZ and PREF from MIPS IV, Fredrik Noring, 2018/09/16
- [Qemu-devel] [PATCH v4 4/8] target/mips: Add function to signal RI exception unless user only, Fredrik Noring, 2018/09/16
- [Qemu-devel] [PATCH v4 5/8] target/mips: R5900 DMULT[U], DDIV[U], LL, SC, LLD and SCD are user only,
Fredrik Noring <=
- [Qemu-devel] [PATCH v4 6/8] target/mips: Define the R5900 CPU, Fredrik Noring, 2018/09/16
- [Qemu-devel] [PATCH v4 7/8] linux-user/mips: Recognise the R5900 CPU model, Fredrik Noring, 2018/09/16
- [Qemu-devel] [PATCH v4 8/8] elf: Toshiba/Sony rather than MIPS are the implementors of the R5900, Fredrik Noring, 2018/09/16
- Re: [Qemu-devel] [PATCH v4 8/8] elf: Toshiba/Sony rather than MIPS are the implementors of the R5900, Philippe Mathieu-Daudé, 2018/09/16
- Re: [Qemu-devel] [PATCH v4 7/8] linux-user/mips: Recognise the R5900 CPU model, Philippe Mathieu-Daudé, 2018/09/16
- Re: [Qemu-devel] [PATCH v4 5/8] target/mips: R5900 DMULT[U], DDIV[U], LL, SC, LLD and SCD are user only, Philippe Mathieu-Daudé, 2018/09/16
- Re: [Qemu-devel] [PATCH v4 5/8] target/mips: R5900 DMULT[U], DDIV[U], LL, SC, LLD and SCD are user only, Maciej W. Rozycki, 2018/09/17
- Re: [Qemu-devel] [PATCH v4 5/8] target/mips: R5900 DMULT[U], DDIV[U], LL, SC, LLD and SCD are user only, Fredrik Noring, 2018/09/18
- Re: [Qemu-devel] [PATCH v4 5/8] target/mips: R5900 DMULT[U], DDIV[U], LL, SC, LLD and SCD are user only, Maciej W. Rozycki, 2018/09/18
- Re: [Qemu-devel] [PATCH v4 5/8] target/mips: R5900 DMULT[U], DDIV[U], LL, SC, LLD and SCD are user only, Philippe Mathieu-Daudé, 2018/09/19