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[Qemu-devel] [PATCH v4 3/8] target/mips: Support R5900 instructions MOVN
From: |
Fredrik Noring |
Subject: |
[Qemu-devel] [PATCH v4 3/8] target/mips: Support R5900 instructions MOVN, MOVZ and PREF from MIPS IV |
Date: |
Sat, 15 Sep 2018 10:43:26 +0200 |
CPU_R5900 is defined as CPU_MIPS3 but it has the MIPS IV instructions
MOVN, MOVZ and PREF as well.
Signed-off-by: Fredrik Noring <address@hidden>
---
target/mips/translate.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index fb571e278e..c35be0053b 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -22402,7 +22402,7 @@ static void decode_opc_special_legacy(CPUMIPSState
*env, DisasContext *ctx)
case OPC_MOVN: /* Conditional move */
case OPC_MOVZ:
check_insn(ctx, ISA_MIPS4 | ISA_MIPS32 |
- INSN_LOONGSON2E | INSN_LOONGSON2F);
+ INSN_LOONGSON2E | INSN_LOONGSON2F | INSN_R5900);
gen_cond_move(ctx, op1, rd, rs, rt);
break;
case OPC_MFHI: /* Move from HI/LO */
@@ -24986,7 +24986,8 @@ static void decode_opc(CPUMIPSState *env, DisasContext
*ctx)
break;
case OPC_PREF:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
- check_insn(ctx, ISA_MIPS4 | ISA_MIPS32);
+ check_insn(ctx, ISA_MIPS4 | ISA_MIPS32 |
+ INSN_R5900);
/* Treat as NOP. */
break;
--
2.16.4
- [Qemu-devel] [PATCH v4 0/8] target/mips: Support R5900 GCC programs in user mode, Fredrik Noring, 2018/09/16
- [Qemu-devel] [PATCH v4 1/8] target/mips: Define R5900 instructions and CPU preprocessor constants, Fredrik Noring, 2018/09/16
- [Qemu-devel] [PATCH v4 2/8] target/mips: Support R5900 specific three-operand MULT and MULTU, Fredrik Noring, 2018/09/16
- [Qemu-devel] [PATCH v4 3/8] target/mips: Support R5900 instructions MOVN, MOVZ and PREF from MIPS IV,
Fredrik Noring <=
- [Qemu-devel] [PATCH v4 4/8] target/mips: Add function to signal RI exception unless user only, Fredrik Noring, 2018/09/16
- [Qemu-devel] [PATCH v4 5/8] target/mips: R5900 DMULT[U], DDIV[U], LL, SC, LLD and SCD are user only, Fredrik Noring, 2018/09/16
- [Qemu-devel] [PATCH v4 6/8] target/mips: Define the R5900 CPU, Fredrik Noring, 2018/09/16
- [Qemu-devel] [PATCH v4 7/8] linux-user/mips: Recognise the R5900 CPU model, Fredrik Noring, 2018/09/16
- [Qemu-devel] [PATCH v4 8/8] elf: Toshiba/Sony rather than MIPS are the implementors of the R5900, Fredrik Noring, 2018/09/16
- Re: [Qemu-devel] [PATCH v4 8/8] elf: Toshiba/Sony rather than MIPS are the implementors of the R5900, Philippe Mathieu-Daudé, 2018/09/16
- Re: [Qemu-devel] [PATCH v4 7/8] linux-user/mips: Recognise the R5900 CPU model, Philippe Mathieu-Daudé, 2018/09/16
- Re: [Qemu-devel] [PATCH v4 5/8] target/mips: R5900 DMULT[U], DDIV[U], LL, SC, LLD and SCD are user only, Philippe Mathieu-Daudé, 2018/09/16
- Re: [Qemu-devel] [PATCH v4 5/8] target/mips: R5900 DMULT[U], DDIV[U], LL, SC, LLD and SCD are user only, Maciej W. Rozycki, 2018/09/17
- Re: [Qemu-devel] [PATCH v4 5/8] target/mips: R5900 DMULT[U], DDIV[U], LL, SC, LLD and SCD are user only, Fredrik Noring, 2018/09/18