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Re: [Qemu-devel] [PATCH 22/28] target/riscv: Move gen_arith_imm() decodi
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH 22/28] target/riscv: Move gen_arith_imm() decoding into trans_* functions |
Date: |
Sat, 13 Oct 2018 12:54:40 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.0 |
On 10/12/18 10:30 AM, Bastian Koppelmann wrote:
> static bool trans_slliw(DisasContext *ctx, arg_slliw *a, uint32_t insn)
> {
> - gen_arith_imm(ctx, OPC_RISC_SLLIW, a->rd, a->rs1, a->shamt);
> + TCGv source1;
> + source1 = tcg_temp_new();
> + gen_get_gpr(source1, a->rs1);
> +
> + tcg_gen_shli_tl(source1, source1, a->shamt);
> + tcg_gen_ext32s_tl(source1, source1);
> + gen_set_gpr(a->rd, source1);
> +
> + tcg_temp_free(source1);
> return true;
> }
Now missing the TARGET_RISCV64 check.
> +static bool trans_arith_imm(DisasContext *ctx, arg_arith_imm *a,
> + void(*func)(TCGv, TCGv, TCGv))
gen_arith_imm.
r~
- Re: [Qemu-devel] [PATCH 23/28] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists, (continued)
- [Qemu-devel] [PATCH 28/28] target/riscv: Replace gen_exception_illegal with return false, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 13/28] target/riscv: Convert RV64D insns to decodetree, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 12/28] target/riscv: Convert RV32D insns to decodetree, Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 20/28] target/riscv: Replace gen_load() with trans_load(), Bastian Koppelmann, 2018/10/12
- [Qemu-devel] [PATCH 22/28] target/riscv: Move gen_arith_imm() decoding into trans_* functions, Bastian Koppelmann, 2018/10/12
- Re: [Qemu-devel] [PATCH 22/28] target/riscv: Move gen_arith_imm() decoding into trans_* functions,
Richard Henderson <=