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[Qemu-devel] [PULL 15/34] target/mips: Placeholder for R5900 MMI2 instru
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL 15/34] target/mips: Placeholder for R5900 MMI2 instruction subclass |
Date: |
Mon, 22 Oct 2018 14:57:38 +0200 |
From: Fredrik Noring <address@hidden>
Add a placeholder for MMI2 subclass.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/translate.c | 40 +++++++++++++++++++++++++++++++++++++++-
1 file changed, 39 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 07e33e0..cc00429 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24491,6 +24491,42 @@ static void decode_tx79_mmi1(CPUMIPSState *env,
DisasContext *ctx)
}
}
+static void decode_tx79_mmi2(CPUMIPSState *env, DisasContext *ctx)
+{
+ uint32_t opc = MASK_TX79_MMI2(ctx->opcode);
+
+ switch (opc) {
+ case TX79_MMI2_PMADDW: /* TODO: TX79_MMI2_PMADDW */
+ case TX79_MMI2_PSLLVW: /* TODO: TX79_MMI2_PSLLVW */
+ case TX79_MMI2_PSRLVW: /* TODO: TX79_MMI2_PSRLVW */
+ case TX79_MMI2_PMSUBW: /* TODO: TX79_MMI2_PMSUBW */
+ case TX79_MMI2_PMFHI: /* TODO: TX79_MMI2_PMFHI */
+ case TX79_MMI2_PMFLO: /* TODO: TX79_MMI2_PMFLO */
+ case TX79_MMI2_PINTH: /* TODO: TX79_MMI2_PINTH */
+ case TX79_MMI2_PMULTW: /* TODO: TX79_MMI2_PMULTW */
+ case TX79_MMI2_PDIVW: /* TODO: TX79_MMI2_PDIVW */
+ case TX79_MMI2_PCPYLD: /* TODO: TX79_MMI2_PCPYLD */
+ case TX79_MMI2_PMADDH: /* TODO: TX79_MMI2_PMADDH */
+ case TX79_MMI2_PHMADH: /* TODO: TX79_MMI2_PHMADH */
+ case TX79_MMI2_PAND: /* TODO: TX79_MMI2_PAND */
+ case TX79_MMI2_PXOR: /* TODO: TX79_MMI2_PXOR */
+ case TX79_MMI2_PMSUBH: /* TODO: TX79_MMI2_PMSUBH */
+ case TX79_MMI2_PHMSBH: /* TODO: TX79_MMI2_PHMSBH */
+ case TX79_MMI2_PEXEH: /* TODO: TX79_MMI2_PEXEH */
+ case TX79_MMI2_PREVH: /* TODO: TX79_MMI2_PREVH */
+ case TX79_MMI2_PMULTH: /* TODO: TX79_MMI2_PMULTH */
+ case TX79_MMI2_PDIVBW: /* TODO: TX79_MMI2_PDIVBW */
+ case TX79_MMI2_PEXEW: /* TODO: TX79_MMI2_PEXEW */
+ case TX79_MMI2_PROT3W: /* TODO: TX79_MMI2_PROT3W */
+ generate_exception_end(ctx, EXCP_RI); /* TODO: TX79_MMI_CLASS_MMI2 */
+ break;
+ default:
+ MIPS_INVAL("TX79 MMI class MMI2");
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+}
+
static void decode_tx79_mmi(CPUMIPSState *env, DisasContext *ctx)
{
uint32_t opc = MASK_TX79_MMI(ctx->opcode);
@@ -24502,10 +24538,12 @@ static void decode_tx79_mmi(CPUMIPSState *env,
DisasContext *ctx)
case TX79_MMI_CLASS_MMI1:
decode_tx79_mmi1(env, ctx);
break;
+ case TX79_MMI_CLASS_MMI2:
+ decode_tx79_mmi2(env, ctx);
+ break;
case TX79_MMI_MADD: /* TODO: TX79_MMI_MADD */
case TX79_MMI_MADDU: /* TODO: TX79_MMI_MADDU */
case TX79_MMI_PLZCW: /* TODO: TX79_MMI_PLZCW */
- case TX79_MMI_CLASS_MMI2: /* TODO: TX79_MMI_CLASS_MMI2 */
case TX79_MMI_MFHI1: /* TODO: TX79_MMI_MFHI1 */
case TX79_MMI_MTHI1: /* TODO: TX79_MMI_MTHI1 */
case TX79_MMI_MFLO1: /* TODO: TX79_MMI_MFLO1 */
--
2.7.4
- [Qemu-devel] [PULL 28/34] tests/tcg/mips: Test R5900 MTLO1 and MTHI1, (continued)
- [Qemu-devel] [PULL 28/34] tests/tcg/mips: Test R5900 MTLO1 and MTHI1, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 22/34] target/mips: R5900 DMULT[U], DDIV[U], LL[D] and SC[D] are user only, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 20/34] target/mips: Support R5900 DIV1 and DIVU1 instructions, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 19/34] target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1 instructions, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 16/34] target/mips: Placeholder for R5900 MMI3 instruction subclass, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 13/34] target/mips: Placeholder for R5900 MMI0 instruction subclass, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 14/34] target/mips: Placeholder for R5900 MMI1 instruction subclass, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 21/34] target/mips: Support R5900 MOVN, MOVZ and PREF instructions from MIPS IV, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 24/34] tests/tcg/mips: Test R5900 three-operand MULTU, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 10/34] target/mips: Placeholder for R5900 SQ, handle user mode RDHWR, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 15/34] target/mips: Placeholder for R5900 MMI2 instruction subclass,
Aleksandar Markovic <=
- [Qemu-devel] [PULL 26/34] tests/tcg/mips: Test R5900 three-operand MULTU1, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 30/34] tests/tcg/mips: Test R5900 DIVU1, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 25/34] tests/tcg/mips: Test R5900 three-operand MULT1, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 29/34] tests/tcg/mips: Test R5900 DIV1, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 31/34] target/mips: Define the R5900 CPU, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 27/34] tests/tcg/mips: Test R5900 MFLO1 and MFHI1, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 32/34] linux-user/mips: Recognise the R5900 CPU model, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 33/34] target/mips: Fix the title of translate.c, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 34/34] target/mips: Fix decoding of ALIGN and DALIGN instructions, Aleksandar Markovic, 2018/10/22
- Re: [Qemu-devel] [PULL 00/34] MIPS queue for October 2018 - part 2, Peter Maydell, 2018/10/23