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[Qemu-devel] [PATCH 1/2] target/mips: Fix decoding mechanism of R5900 MF
From: |
Fredrik Noring |
Subject: |
[Qemu-devel] [PATCH 1/2] target/mips: Fix decoding mechanism of R5900 MFLO1, MFHI1, MTLO1 and MTHI1 |
Date: |
Fri, 2 Nov 2018 17:08:17 +0100 |
User-agent: |
Mutt/1.10.1 (2018-07-13) |
MFLO1, MFHI1, MTLO1 and MTHI1 are generated in gen_HILO1_tx79 instead of
the generic gen_HILO.
Signed-off-by: Fredrik Noring <address@hidden>
---
target/mips/translate.c | 67 ++++++++++++++++++++++++++++++++++-------
1 file changed, 56 insertions(+), 11 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 60320cbe69..f3993cf7d7 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -4359,24 +4359,72 @@ static void gen_shift(DisasContext *ctx, uint32_t opc,
tcg_temp_free(t1);
}
+/* Move to and from TX79 HI1/LO1 registers. */
+static void gen_HILO1_tx79(DisasContext *ctx, uint32_t opc, int reg)
+{
+ if (reg == 0 && (opc == TX79_MMI_MFHI1 || opc == TX79_MMI_MFLO1)) {
+ /* Treat as NOP. */
+ return;
+ }
+
+ switch (opc) {
+ case TX79_MMI_MFHI1:
+#if defined(TARGET_MIPS64)
+ tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_HI[1]);
+#else
+ tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[1]);
+#endif
+ break;
+ case TX79_MMI_MFLO1:
+#if defined(TARGET_MIPS64)
+ tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_LO[1]);
+#else
+ tcg_gen_mov_tl(cpu_gpr[reg], cpu_LO[1]);
+#endif
+ break;
+ case TX79_MMI_MTHI1:
+ if (reg != 0) {
+#if defined(TARGET_MIPS64)
+ tcg_gen_ext32s_tl(cpu_HI[1], cpu_gpr[reg]);
+#else
+ tcg_gen_mov_tl(cpu_HI[1], cpu_gpr[reg]);
+#endif
+ } else {
+ tcg_gen_movi_tl(cpu_HI[1], 0);
+ }
+ break;
+ case TX79_MMI_MTLO1:
+ if (reg != 0) {
+#if defined(TARGET_MIPS64)
+ tcg_gen_ext32s_tl(cpu_LO[1], cpu_gpr[reg]);
+#else
+ tcg_gen_mov_tl(cpu_LO[1], cpu_gpr[reg]);
+#endif
+ } else {
+ tcg_gen_movi_tl(cpu_LO[1], 0);
+ }
+ break;
+ default:
+ MIPS_INVAL("MFTHILO TX79");
+ generate_exception_end(ctx, EXCP_RI);
+ break;
+ }
+}
+
/* Arithmetic on HI/LO registers */
static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg)
{
- if (reg == 0 && (opc == OPC_MFHI || opc == TX79_MMI_MFHI1 ||
- opc == OPC_MFLO || opc == TX79_MMI_MFLO1)) {
+ if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) {
/* Treat as NOP. */
return;
}
if (acc != 0) {
- if (!(ctx->insn_flags & INSN_R5900)) {
- check_dsp(ctx);
- }
+ check_dsp(ctx);
}
switch (opc) {
case OPC_MFHI:
- case TX79_MMI_MFHI1:
#if defined(TARGET_MIPS64)
if (acc != 0) {
tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_HI[acc]);
@@ -4387,7 +4435,6 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc, int
acc, int reg)
}
break;
case OPC_MFLO:
- case TX79_MMI_MFLO1:
#if defined(TARGET_MIPS64)
if (acc != 0) {
tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_LO[acc]);
@@ -4398,7 +4445,6 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc, int
acc, int reg)
}
break;
case OPC_MTHI:
- case TX79_MMI_MTHI1:
if (reg != 0) {
#if defined(TARGET_MIPS64)
if (acc != 0) {
@@ -4413,7 +4459,6 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc, int
acc, int reg)
}
break;
case OPC_MTLO:
- case TX79_MMI_MTLO1:
if (reg != 0) {
#if defined(TARGET_MIPS64)
if (acc != 0) {
@@ -26500,11 +26545,11 @@ static void decode_tx79_mmi(CPUMIPSState *env,
DisasContext *ctx)
break;
case TX79_MMI_MTLO1:
case TX79_MMI_MTHI1:
- gen_HILO(ctx, opc, 1, rs);
+ gen_HILO1_tx79(ctx, opc, rs);
break;
case TX79_MMI_MFLO1:
case TX79_MMI_MFHI1:
- gen_HILO(ctx, opc, 1, rd);
+ gen_HILO1_tx79(ctx, opc, rd);
break;
case TX79_MMI_MADD: /* TODO: TX79_MMI_MADD */
case TX79_MMI_MADDU: /* TODO: TX79_MMI_MADDU */
--
2.18.1
- [Qemu-devel] [PATCH 0/2] target/mips: Fix decoding mechanisms of R5900 M{F, T}{HI, LO}1 and DIV[U]1, Fredrik Noring, 2018/11/02
- [Qemu-devel] [PATCH 2/2] target/mips: Fix decoding mechanism of R5900 DIV1 and DIVU1, Fredrik Noring, 2018/11/02
- [Qemu-devel] [PATCH 1/2] target/mips: Fix decoding mechanism of R5900 MFLO1, MFHI1, MTLO1 and MTHI1,
Fredrik Noring <=
- Re: [Qemu-devel] [PATCH 1/2] target/mips: Fix decoding mechanism of R5900 MFLO1, MFHI1, MTLO1 and MTHI1, Philippe Mathieu-Daudé, 2018/11/02
- Re: [Qemu-devel] [PATCH 1/2] target/mips: Fix decoding mechanism of R5900 MFLO1, MFHI1, MTLO1 and MTHI1, Richard Henderson, 2018/11/04
- Re: [Qemu-devel] [PATCH 1/2] target/mips: Fix decoding mechanism of R5900 MFLO1, MFHI1, MTLO1 and MTHI1, Fredrik Noring, 2018/11/04
- Re: [Qemu-devel] [PATCH 1/2] target/mips: Fix decoding mechanism of R5900 MFLO1, MFHI1, MTLO1 and MTHI1, Maciej W. Rozycki, 2018/11/04
- Re: [Qemu-devel] [PATCH 1/2] target/mips: Fix decoding mechanism of R5900 MFLO1, MFHI1, MTLO1 and MTHI1, Fredrik Noring, 2018/11/05
- Re: [Qemu-devel] [PATCH 1/2] target/mips: Fix decoding mechanism of R5900 MFLO1, MFHI1, MTLO1 and MTHI1, Maciej W. Rozycki, 2018/11/05
Re: [Qemu-devel] [PATCH 0/2] target/mips: Fix decoding mechanisms of R5900 M{F, T}{HI, LO}1 and DIV[U]1, Aleksandar Markovic, 2018/11/05