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Re: [Qemu-ppc] [Qemu-devel] [PATCH 07/18] target-ppc: Add ISA 2.06 stbcx
From: |
Richard Henderson |
Subject: |
Re: [Qemu-ppc] [Qemu-devel] [PATCH 07/18] target-ppc: Add ISA 2.06 stbcx. and sthcx. Instructions |
Date: |
Mon, 09 Dec 2013 16:41:44 -0800 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.1.0 |
On 12/09/2013 07:47 AM, Tom Musta wrote:
> -static void gen_conditional_store (DisasContext *ctx, TCGv EA,
> +static void gen_conditional_store(DisasContext *ctx, TCGv EA,
> int reg, int size)
If you're going to make random changes to the formatting, fix it all -- the
indentation on the next line is now wrong.
> + gen_qemu_##storeop(ctx, cpu_gpr[rS(ctx->opcode)], t0); \
I meant to mention this for l*arx too, but please use the new ldst opcodes.
That'll save me having to make the change here in the next couple of weeks.
Also, surely better to implement gen_conditional_store !USER, instead of
duplicating the STCX macro.
r~
[Qemu-ppc] [PATCH 08/18] target-ppc: Add ISA2.06 Float to Integer Instructions, Tom Musta, 2013/12/09
[Qemu-ppc] [PATCH 10/18] softfloat: Fix float64_to_uint64_round_to_zero, Tom Musta, 2013/12/09
[Qemu-ppc] [PATCH 11/18] softfloat: Fix float64_to_uint32, Tom Musta, 2013/12/09
[Qemu-ppc] [PATCH 12/18] softfloat: Fix float64_to_uint32_round_to_zero, Tom Musta, 2013/12/09
[Qemu-ppc] [PATCH 13/18] target-ppc: Add ISA 2.06 fcfid[u][s] Instructions, Tom Musta, 2013/12/09