[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-ppc] [PULL 26/32] Add xxspltw
From: |
Alexander Graf |
Subject: |
[Qemu-ppc] [PULL 26/32] Add xxspltw |
Date: |
Fri, 20 Dec 2013 02:00:48 +0100 |
From: Tom Musta <address@hidden>
This patch adds the VSX Splat Word (xxsplatw) instruction.
This is the first instruction to use the UIM immediate field
and consequently a decoder is also added.
V2: reworked implementation per Richard Henderson's comments.
Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
---
target-ppc/translate.c | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index e5d7f9d..f342468 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -499,6 +499,7 @@ EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
EXTRACT_HELPER(DM, 8, 2);
+EXTRACT_HELPER(UIM, 16, 2);
/*****************************************************************************/
/* PowerPC instructions table */
@@ -7358,6 +7359,35 @@ static void gen_xxsel(DisasContext * ctx)
tcg_temp_free(c);
}
+static void gen_xxspltw(DisasContext *ctx)
+{
+ TCGv_i64 b, b2;
+ TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ?
+ cpu_vsrl(xB(ctx->opcode)) :
+ cpu_vsrh(xB(ctx->opcode));
+
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+
+ b = tcg_temp_new();
+ b2 = tcg_temp_new();
+
+ if (UIM(ctx->opcode) & 1) {
+ tcg_gen_ext32u_i64(b, vsr);
+ } else {
+ tcg_gen_shri_i64(b, vsr, 32);
+ }
+
+ tcg_gen_shli_i64(b2, b, 32);
+ tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2);
+ tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
+
+ tcg_temp_free(b);
+ tcg_temp_free(b2);
+}
+
/*** SPE extension ***/
/* Register moves */
@@ -9872,6 +9902,7 @@ VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
+GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
#define GEN_XXSEL_ROW(opc3) \
GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
--
1.8.1.4
- [Qemu-ppc] [PULL 10/32] Add lxsdx, (continued)
- [Qemu-ppc] [PULL 10/32] Add lxsdx, Alexander Graf, 2013/12/19
- [Qemu-ppc] [PULL 09/32] Add xxpermdi, Alexander Graf, 2013/12/19
- [Qemu-ppc] [PULL 13/32] Add stxsdx, Alexander Graf, 2013/12/19
- [Qemu-ppc] [PULL 12/32] Add lxvw4x, Alexander Graf, 2013/12/19
- [Qemu-ppc] [PULL 15/32] target-ppc: move POWER7+ to a separate family, Alexander Graf, 2013/12/19
- [Qemu-ppc] [PULL 23/32] Add Power7 VSX Logical Instructions, Alexander Graf, 2013/12/19
- [Qemu-ppc] [PULL 31/32] spapr: make sure RMA is in first mode of first memory node, Alexander Graf, 2013/12/19
- [Qemu-ppc] [PULL 17/32] spapr-rtas: add ibm, (get|set)-system-parameter, Alexander Graf, 2013/12/19
- [Qemu-ppc] [PULL 19/32] spapr: tie spapr-nvram to -pflash, Alexander Graf, 2013/12/19
- [Qemu-ppc] [PULL 18/32] PPC: Use default pci bus name for grackle and heathrow, Alexander Graf, 2013/12/19
- [Qemu-ppc] [PULL 26/32] Add xxspltw,
Alexander Graf <=
- [Qemu-ppc] [PULL 28/32] PPC: Add VSX to hflags, Alexander Graf, 2013/12/19
- [Qemu-ppc] [PULL 16/32] spapr-rtas: replace return code constants with macros, Alexander Graf, 2013/12/19
- [Qemu-ppc] [PULL 32/32] spapr: limit numa memory regions by ram size, Alexander Graf, 2013/12/19
- [Qemu-ppc] [PULL 29/32] device_tree: s/qemu_devtree/qemu_fdt globally, Alexander Graf, 2013/12/19
- [Qemu-ppc] [PULL 25/32] Add xxsel, Alexander Graf, 2013/12/19
- [Qemu-ppc] [PULL 27/32] Add xxsldwi, Alexander Graf, 2013/12/19
- [Qemu-ppc] [PULL 21/32] Add VSX Scalar Move Instructions, Alexander Graf, 2013/12/19
- [Qemu-ppc] [PULL 30/32] device_tree: qemu_fdt_setprop: Rename val_array arg, Alexander Graf, 2013/12/19