[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-riscv] [PATCH v7 29/35] target/riscv: Remove gen_system()
From: |
Palmer Dabbelt |
Subject: |
[Qemu-riscv] [PATCH v7 29/35] target/riscv: Remove gen_system() |
Date: |
Wed, 13 Feb 2019 07:54:08 -0800 |
From: Bastian Koppelmann <address@hidden>
with all 16 bit insns moved to decodetree no path is falling back to
gen_system(), so we can remove it.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>
---
target/riscv/translate.c | 34 ----------------------------------
1 file changed, 34 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 3d49c8ed4054..65bedc966497 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -474,33 +474,6 @@ static void gen_set_rm(DisasContext *ctx, int rm)
tcg_temp_free_i32(t0);
}
-static void gen_system(DisasContext *ctx, uint32_t opc, int rd, int rs1,
- int csr)
-{
- tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
-
- switch (opc) {
- case OPC_RISC_ECALL:
- switch (csr) {
- case 0x0: /* ECALL */
- /* always generates U-level ECALL, fixed in do_interrupt handler */
- generate_exception(ctx, RISCV_EXCP_U_ECALL);
- tcg_gen_exit_tb(NULL, 0); /* no chaining */
- ctx->base.is_jmp = DISAS_NORETURN;
- break;
- case 0x1: /* EBREAK */
- generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
- tcg_gen_exit_tb(NULL, 0); /* no chaining */
- ctx->base.is_jmp = DISAS_NORETURN;
- break;
- default:
- gen_exception_illegal(ctx);
- break;
- }
- break;
- }
-}
-
static void decode_RV32_64C0(DisasContext *ctx)
{
uint8_t funct3 = extract32(ctx->opcode, 13, 3);
@@ -675,7 +648,6 @@ bool decode_insn16(DisasContext *ctx, uint16_t insn);
static void decode_RV32_64G(DisasContext *ctx)
{
- int rs1, rd;
uint32_t op;
/* We do not do misaligned address check here: the address should never be
@@ -684,14 +656,8 @@ static void decode_RV32_64G(DisasContext *ctx)
* perform the misaligned instruction fetch */
op = MASK_OP_MAJOR(ctx->opcode);
- rs1 = GET_RS1(ctx->opcode);
- rd = GET_RD(ctx->opcode);
switch (op) {
- case OPC_RISC_SYSTEM:
- gen_system(ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1,
- (ctx->opcode & 0xFFF00000) >> 20);
- break;
default:
gen_exception_illegal(ctx);
break;
--
2.18.1
- [Qemu-riscv] [PATCH v7 08/35] target/riscv: Convert RVXI csr insns to decodetree, (continued)
- [Qemu-riscv] [PATCH v7 08/35] target/riscv: Convert RVXI csr insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 10/35] target/riscv: Convert RV32A insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 17/35] target/riscv: Convert quadrant 0 of RVXC insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 20/35] target/riscv: Remove gen_jalr(), Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 06/35] target/riscv: Convert RVXI arithmetic insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 19/35] target/riscv: Convert quadrant 2 of RVXC insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 11/35] target/riscv: Convert RV64A insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 13/35] target/riscv: Convert RV64F insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 29/35] target/riscv: Remove gen_system(),
Palmer Dabbelt <=
- [Qemu-riscv] [PATCH v7 07/35] target/riscv: Convert RVXI fence insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 03/35] target/riscv: Convert RVXI branch insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 09/35] target/riscv: Convert RVXM insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 05/35] target/riscv: Convert RV64I load/store insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 23/35] target/riscv: Remove manual decoding from gen_store(), Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 22/35] target/riscv: Remove manual decoding from gen_load(), Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 21/35] target/riscv: Remove manual decoding from gen_branch(), Palmer Dabbelt, 2019/02/13