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[Qemu-riscv] [PATCH v7 09/35] target/riscv: Convert RVXM insns to decode
From: |
Palmer Dabbelt |
Subject: |
[Qemu-riscv] [PATCH v7 09/35] target/riscv: Convert RVXM insns to decodetree |
Date: |
Wed, 13 Feb 2019 07:53:48 -0800 |
From: Bastian Koppelmann <address@hidden>
Acked-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>
---
target/riscv/insn32-64.decode | 7 ++
target/riscv/insn32.decode | 10 +++
target/riscv/insn_trans/trans_rvm.inc.c | 100 ++++++++++++++++++++++++
target/riscv/translate.c | 10 +--
4 files changed, 118 insertions(+), 9 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_rvm.inc.c
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode
index 9a35f2aa1920..008f1005469e 100644
--- a/target/riscv/insn32-64.decode
+++ b/target/riscv/insn32-64.decode
@@ -36,3 +36,10 @@ subw 0100000 ..... ..... 000 ..... 0111011 @r
sllw 0000000 ..... ..... 001 ..... 0111011 @r
srlw 0000000 ..... ..... 101 ..... 0111011 @r
sraw 0100000 ..... ..... 101 ..... 0111011 @r
+
+# *** RV64M Standard Extension (in addition to RV32M) ***
+mulw 0000001 ..... ..... 000 ..... 0111011 @r
+divw 0000001 ..... ..... 100 ..... 0111011 @r
+divuw 0000001 ..... ..... 101 ..... 0111011 @r
+remw 0000001 ..... ..... 110 ..... 0111011 @r
+remuw 0000001 ..... ..... 111 ..... 0111011 @r
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 977b1b10a330..e53944bf0e40 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -92,3 +92,13 @@ csrrc ............ ..... 011 ..... 1110011 @csr
csrrwi ............ ..... 101 ..... 1110011 @csr
csrrsi ............ ..... 110 ..... 1110011 @csr
csrrci ............ ..... 111 ..... 1110011 @csr
+
+# *** RV32M Standard Extension ***
+mul 0000001 ..... ..... 000 ..... 0110011 @r
+mulh 0000001 ..... ..... 001 ..... 0110011 @r
+mulhsu 0000001 ..... ..... 010 ..... 0110011 @r
+mulhu 0000001 ..... ..... 011 ..... 0110011 @r
+div 0000001 ..... ..... 100 ..... 0110011 @r
+divu 0000001 ..... ..... 101 ..... 0110011 @r
+rem 0000001 ..... ..... 110 ..... 0110011 @r
+remu 0000001 ..... ..... 111 ..... 0110011 @r
diff --git a/target/riscv/insn_trans/trans_rvm.inc.c
b/target/riscv/insn_trans/trans_rvm.inc.c
new file mode 100644
index 000000000000..ec3197ede815
--- /dev/null
+++ b/target/riscv/insn_trans/trans_rvm.inc.c
@@ -0,0 +1,100 @@
+/*
+ * RISC-V translation routines for the RV64M Standard Extension.
+ *
+ * Copyright (c) 2016-2017 Sagar Karandikar, address@hidden
+ * Copyright (c) 2018 Peer Adelt, address@hidden
+ * Bastian Koppelmann, address@hidden
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+static bool trans_mul(DisasContext *ctx, arg_mul *a)
+{
+ gen_arith(ctx, OPC_RISC_MUL, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_mulh(DisasContext *ctx, arg_mulh *a)
+{
+ gen_arith(ctx, OPC_RISC_MULH, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_mulhsu(DisasContext *ctx, arg_mulhsu *a)
+{
+ gen_arith(ctx, OPC_RISC_MULHSU, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_mulhu(DisasContext *ctx, arg_mulhu *a)
+{
+ gen_arith(ctx, OPC_RISC_MULHU, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_div(DisasContext *ctx, arg_div *a)
+{
+ gen_arith(ctx, OPC_RISC_DIV, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_divu(DisasContext *ctx, arg_divu *a)
+{
+ gen_arith(ctx, OPC_RISC_DIVU, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_rem(DisasContext *ctx, arg_rem *a)
+{
+ gen_arith(ctx, OPC_RISC_REM, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_remu(DisasContext *ctx, arg_remu *a)
+{
+ gen_arith(ctx, OPC_RISC_REMU, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+#ifdef TARGET_RISCV64
+static bool trans_mulw(DisasContext *ctx, arg_mulw *a)
+{
+ gen_arith(ctx, OPC_RISC_MULW, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_divw(DisasContext *ctx, arg_divw *a)
+{
+ gen_arith(ctx, OPC_RISC_DIVW, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_divuw(DisasContext *ctx, arg_divuw *a)
+{
+ gen_arith(ctx, OPC_RISC_DIVUW, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_remw(DisasContext *ctx, arg_remw *a)
+{
+ gen_arith(ctx, OPC_RISC_REMW, a->rd, a->rs1, a->rs2);
+ return true;
+}
+
+static bool trans_remuw(DisasContext *ctx, arg_remuw *a)
+{
+ gen_arith(ctx, OPC_RISC_REMUW, a->rd, a->rs1, a->rs2);
+ return true;
+}
+#endif
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 395cc2d63626..4e59560ae0b7 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1847,6 +1847,7 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn);
#include "decode_insn32.inc.c"
/* Include insn module translation function */
#include "insn_trans/trans_rvi.inc.c"
+#include "insn_trans/trans_rvm.inc.c"
static void decode_RV32_64G(DisasContext *ctx)
{
@@ -1868,15 +1869,6 @@ static void decode_RV32_64G(DisasContext *ctx)
imm = GET_IMM(ctx->opcode);
switch (op) {
- case OPC_RISC_ARITH:
-#if defined(TARGET_RISCV64)
- case OPC_RISC_ARITH_W:
-#endif
- if (rd == 0) {
- break; /* NOP */
- }
- gen_arith(ctx, MASK_OP_ARITH(ctx->opcode), rd, rs1, rs2);
- break;
case OPC_RISC_FP_LOAD:
gen_fp_load(ctx, MASK_OP_FP_LOAD(ctx->opcode), rd, rs1, imm);
break;
--
2.18.1
- [Qemu-riscv] [PATCH v7 17/35] target/riscv: Convert quadrant 0 of RVXC insns to decodetree, (continued)
- [Qemu-riscv] [PATCH v7 17/35] target/riscv: Convert quadrant 0 of RVXC insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 20/35] target/riscv: Remove gen_jalr(), Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 06/35] target/riscv: Convert RVXI arithmetic insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 19/35] target/riscv: Convert quadrant 2 of RVXC insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 11/35] target/riscv: Convert RV64A insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 13/35] target/riscv: Convert RV64F insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 29/35] target/riscv: Remove gen_system(), Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 07/35] target/riscv: Convert RVXI fence insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 03/35] target/riscv: Convert RVXI branch insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 09/35] target/riscv: Convert RVXM insns to decodetree,
Palmer Dabbelt <=
- [Qemu-riscv] [PATCH v7 25/35] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 05/35] target/riscv: Convert RV64I load/store insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 23/35] target/riscv: Remove manual decoding from gen_store(), Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 22/35] target/riscv: Remove manual decoding from gen_load(), Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 21/35] target/riscv: Remove manual decoding from gen_branch(), Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 15/35] target/riscv: Convert RV64D insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 32/35] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns, Palmer Dabbelt, 2019/02/13
- [Qemu-riscv] [PATCH v7 26/35] target/riscv: Remove shift and slt insn manual decoding, Palmer Dabbelt, 2019/02/13