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Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to
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Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree |
Date: |
Wed, 27 Feb 2019 10:57:33 -0800 (PST) |
Patchew URL: https://patchew.org/QEMU/address@hidden/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: address@hidden
Subject: [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/address@hidden -> patchew/address@hidden
Switched to a new branch 'test'
5bd083629e target/riscv: Remaining rvc insn reuse 32 bit translators
5d72035128 target/riscv: Splice remaining compressed insn pairs for riscv32 vs
riscv64
6efccbbf2a target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
d6cf7db52b target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
3766a76f4d target/riscv: Convert @cs_2 insns to share translation functions
4846b3b328 target/riscv: Remove decode_RV32_64G()
0efdd389e2 target/riscv: Remove gen_system()
1097339ff1 target/riscv: Rename trans_arith to gen_arith
d518ed9ce5 target/riscv: Remove manual decoding of RV32/64M insn
cf2623e4b3 target/riscv: Remove shift and slt insn manual decoding
2635d088f7 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
6f2c427160 target/riscv: Move gen_arith_imm() decoding into trans_* functions
596eac69db target/riscv: Remove manual decoding from gen_store()
fbe9c08387 target/riscv: Remove manual decoding from gen_load()
211fa9a152 target/riscv: Remove manual decoding from gen_branch()
4ed5565c22 target/riscv: Remove gen_jalr()
c847376422 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
9e3cc3766e target/riscv: Convert quadrant 1 of RVXC insns to decodetree
651687752b target/riscv: Convert quadrant 0 of RVXC insns to decodetree
58fa4668be target/riscv: Convert RV priv insns to decodetree
d73e26f036 target/riscv: Convert RV64D insns to decodetree
ad0be02a09 target/riscv: Convert RV32D insns to decodetree
10ed1c1d9b target/riscv: Convert RV64F insns to decodetree
b362a9b73c target/riscv: Convert RV32F insns to decodetree
07503d6299 target/riscv: Convert RV64A insns to decodetree
d6d96c8381 target/riscv: Convert RV32A insns to decodetree
6af83fc00f target/riscv: Convert RVXM insns to decodetree
bb39198396 target/riscv: Convert RVXI csr insns to decodetree
a18e334328 target/riscv: Convert RVXI fence insns to decodetree
84adb8041d target/riscv: Convert RVXI arithmetic insns to decodetree
0a2859982c target/riscv: Convert RV64I load/store insns to decodetree
f931362647 target/riscv: Convert RV32I load/store insns to decodetree
193ee2c237 target/riscv: Convert RVXI branch insns to decodetree
cc59f4df66 target/riscv: Activate decodetree and implemnt LUI & AUIPC
=== OUTPUT BEGIN ===
1/34 Checking commit cc59f4df66ac (target/riscv: Activate decodetree and
implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1884:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 1/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
2/34 Checking commit 193ee2c237c0 (target/riscv: Convert RVXI branch insns to
decodetree)
3/34 Checking commit f9313626470d (target/riscv: Convert RV32I load/store insns
to decodetree)
4/34 Checking commit 0a2859982c91 (target/riscv: Convert RV64I load/store insns
to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 4/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
5/34 Checking commit 84adb8041d3b (target/riscv: Convert RVXI arithmetic insns
to decodetree)
6/34 Checking commit a18e33432833 (target/riscv: Convert RVXI fence insns to
decodetree)
7/34 Checking commit bb3919839612 (target/riscv: Convert RVXI csr insns to
decodetree)
8/34 Checking commit 6af83fc00f55 (target/riscv: Convert RVXM insns to
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 169 lines checked
Patch 8/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
9/34 Checking commit d6d96c838102 (target/riscv: Convert RV32A insns to
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 199 lines checked
Patch 9/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/34 Checking commit 07503d6299f8 (target/riscv: Convert RV64A insns to
decodetree)
11/34 Checking commit b362a9b73c2e (target/riscv: Convert RV32F insns to
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 442 lines checked
Patch 11/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
12/34 Checking commit 10ed1c1d9b25 (target/riscv: Convert RV64F insns to
decodetree)
13/34 Checking commit ad0be02a0922 (target/riscv: Convert RV32D insns to
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 398 lines checked
Patch 13/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
14/34 Checking commit d73e26f0361e (target/riscv: Convert RV64D insns to
decodetree)
15/34 Checking commit 58fa4668be36 (target/riscv: Convert RV priv insns to
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 15/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
16/34 Checking commit 651687752b1a (target/riscv: Convert quadrant 0 of RVXC
insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#251: FILE: target/riscv/translate.c:1072:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 231 lines checked
Patch 16/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/34 Checking commit 9e3cc3766ee8 (target/riscv: Convert quadrant 1 of RVXC
insns to decodetree)
18/34 Checking commit c8473764223a (target/riscv: Convert quadrant 2 of RVXC
insns to decodetree)
19/34 Checking commit 4ed5565c22d6 (target/riscv: Remove gen_jalr())
20/34 Checking commit 211fa9a15238 (target/riscv: Remove manual decoding from
gen_branch())
21/34 Checking commit fbe9c08387c3 (target/riscv: Remove manual decoding from
gen_load())
22/34 Checking commit 596eac69dbd9 (target/riscv: Remove manual decoding from
gen_store())
23/34 Checking commit 6f2c42716035 (target/riscv: Move gen_arith_imm() decoding
into trans_* functions)
24/34 Checking commit 2635d088f707 (target/riscv: make ADD/SUB/OR/XOR/AND insn
use arg lists)
25/34 Checking commit cf2623e4b3df (target/riscv: Remove shift and slt insn
manual decoding)
26/34 Checking commit d518ed9ce5c9 (target/riscv: Remove manual decoding of
RV32/64M insn)
27/34 Checking commit 1097339ff18d (target/riscv: Rename trans_arith to
gen_arith)
28/34 Checking commit 0efdd389e281 (target/riscv: Remove gen_system())
29/34 Checking commit 4846b3b328ee (target/riscv: Remove decode_RV32_64G())
30/34 Checking commit 3766a76f4d1a (target/riscv: Convert @cs_2 insns to share
translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:548:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 30/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
31/34 Checking commit d6cf7db52bbb (target/riscv: Convert @cl_d, @cl_w, @cs_d,
@cs_w insns)
32/34 Checking commit 6efccbbf2a77 (target/riscv: Splice fsw_sd and flw_ld for
riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 309 lines checked
Patch 32/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
33/34 Checking commit 5d720351288e (target/riscv: Splice remaining compressed
insn pairs for riscv32 vs riscv64)
34/34 Checking commit 5bd083629e0f (target/riscv: Remaining rvc insn reuse 32
bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/address@hidden/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to address@hidden
- [Qemu-riscv] [PATCH v8 32/34] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64, (continued)
- [Qemu-riscv] [PATCH v8 32/34] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64, Bastian Koppelmann, 2019/02/22
- [Qemu-riscv] [PATCH v8 24/34] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists, Bastian Koppelmann, 2019/02/22
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, Alistair Francis, 2019/02/22
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree,
no-reply <=
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27