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[Qemu-stable] [PULL 03/15] tcg/optimize: fix known-zero bits for right s
From: |
Richard Henderson |
Subject: |
[Qemu-stable] [PULL 03/15] tcg/optimize: fix known-zero bits for right shift ops |
Date: |
Mon, 17 Feb 2014 19:15:53 -0600 |
From: Aurelien Jarno <address@hidden>
32-bit versions of sar and shr ops should not propagate known-zero bits
from the unused 32 high bits. For sar it could even lead to wrong code
being generated.
Cc: address@hidden
Reviewed-by: Paolo Bonzini <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/optimize.c | 19 ++++++++++++++-----
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 89e2d6a..c5cdde2 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -726,16 +726,25 @@ static TCGArg *tcg_constant_folding(TCGContext *s,
uint16_t *tcg_opc_ptr,
mask = temps[args[1]].mask & mask;
break;
- CASE_OP_32_64(sar):
+ case INDEX_op_sar_i32:
+ if (temps[args[2]].state == TCG_TEMP_CONST) {
+ mask = (int32_t)temps[args[1]].mask >> temps[args[2]].val;
+ }
+ break;
+ case INDEX_op_sar_i64:
if (temps[args[2]].state == TCG_TEMP_CONST) {
- mask = ((tcg_target_long)temps[args[1]].mask
- >> temps[args[2]].val);
+ mask = (int64_t)temps[args[1]].mask >> temps[args[2]].val;
}
break;
- CASE_OP_32_64(shr):
+ case INDEX_op_shr_i32:
+ if (temps[args[2]].state == TCG_TEMP_CONST) {
+ mask = (uint32_t)temps[args[1]].mask >> temps[args[2]].val;
+ }
+ break;
+ case INDEX_op_shr_i64:
if (temps[args[2]].state == TCG_TEMP_CONST) {
- mask = temps[args[1]].mask >> temps[args[2]].val;
+ mask = (uint64_t)temps[args[1]].mask >> temps[args[2]].val;
}
break;
--
1.8.5.3
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