Re: [Simulavr-devel] Patch: simulavrxx <->Verilog binding

[Klaus Rudolph]

Hi Onno,

I need your help for building the verliog things!

First of all:
The patch to the sources are fine, after finsihing the build system 
problems I will commit them.

The build:
If I build the verlig-vpi with your method, you will catch a libbfd.so 
file which is possibly not related to avr and
also could diver in version from installed bfd on the system. this will 
result in the following problems:
If system libbfd is compatible to the avr-libbfd all is fine. But on my 
installation (linux-i386) that is not true!
This will result in a dump!

How I fixed that on my machine:
I have a tmp directory which contains all needed .o files from 
libbfd/libiberty, simply catched from archive
with ar x *.la command.
After that I have a line in a hand crafted Makefile like this:

iverilog-vpi  --name=avr $(OBJECTS) $(BFDOBJECTS) vpi.o -lc -lm

where the OBJECTS the same as for other targets in the project like for 
simulavr.
BFDOBJECTS is simply the list of all *.o files in my local tmp directory 
where I un-archived the libbfd/libiberty.

After that trick I was able to run your verilog glue code and could 
generate the *.vcd files.
GREAT :-)
But what I see in the gtkwave makes no sense for me.... ???
The output for portb/pinb is 01/00/02/00/04 and so on.... this has no 
relation the the program, or? :-)
Could you explain that for me please... :-)

So what should we do to get the things play:
Please find out how to link against the correct libbfd/libiberty. If not 
possible (I have searched arround 2 hours :-( )
bring the tmp-object-dir to the build-system. I am not an expert of 
autotools at all. But I hope that there is a trick
in the varilog commands to link against correct libs. Attention: there 
is no libbfd.so in the standard avr-compilation. Maybe there
is a trick how to get them and this should be documented.
After that I will verify the build-toolchain and check your changes in.
And yes: could you send a smart documentation how to use the simulavrxx 
into verilog for beginners (like me:-)
And another question: Is it possible to attatch gdb while runnung 
verilog and have online graphs and maybe able to stimulate
pins from a tool inside the verlilog... as you can see: I have no idea 
what verilog can do for us! :-)


Where could I start reading in using verilog? :-)

Thanks
Klaus