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RE: [avr-gcc-list] gcc prolog incorrect?

From: Larry Barello
Subject: RE: [avr-gcc-list] gcc prolog incorrect?
Date: Mon, 7 Mar 2005 06:19:46 -0800

I didn't think this was a wart due to the pipeline.  I thought it was by
design, otherwise you would never be able to single step through code using
software interrupts (i.e. set up a timer, or twiddle an INTx bit):  A s/w
debugger needs to be able to execute at least one instruction after the
'reti' before re-entering the debug handler.

Note, *all* instructions that restore the I bit, regardless of their cycle
time, delay actually changing the state until after the next instruction,
again, regardless of the cycle timing.  reti takes what, four cycles?  cli &
out SREG take one?  You can even "sts SREG+0x20, " (3 cycles) or "st x," (2
cycles) to SREG via memory instead of I/O and get the same effect.


-----Original Message-----
From: address@hidden
[mailto:address@hidden Behalf
Of Ben L. Titzer
Sent: Sunday, March 06, 2005 8:19 PM
Cc: address@hidden
Subject: Re: [avr-gcc-list] gcc prolog incorrect?

On Mar 6, 2005, at 7:46 PM, Jeff Barlow wrote:

> "Ben L. Titzer" <address@hidden>  wrote:
>> The thing I wonder about is what happens if there is an interrupt
>> between 72 and 73....It seems to me that those two instructions should
>> be swapped...
> And your homework assignment is to read that part of the Atmel
> datasheet very carefully. Hint: we get one free.
> BTW, you're right about the interrupt enable flag being saved
> correctly.

Oh no! Trick question--neither the datasheet nor the instruction set
specification directly answers this question. The answer is buried in
the pipeline description and the cycle counts of the respective
instructions--i.e. when 72 is executing, 73 is already being fetched,
and since the I flag was disabled by the CLI previously, there will be
no interrupts between 72 and 73 because the effect of 72 isn't checked
until 74 is being fetched...

Wonderful. I guess I am going to have to fix this in Avrora with some
ugly kludge...

And here I thought the pipeline was not visible above the
micro-architecture level....thanks Atmel.

> --
> Later,
> Jeff
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