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RE: [avr-gcc-list] Toolchain developers: State of GCC HEAD

From: Weddington, Eric
Subject: RE: [avr-gcc-list] Toolchain developers: State of GCC HEAD
Date: Tue, 26 Aug 2008 14:31:52 -0600


> -----Original Message-----
> From: address@hidden [mailto:address@hidden 
> Sent: Tuesday, August 26, 2008 2:12 PM
> To: Weddington, Eric; address@hidden
> Subject: Re: [avr-gcc-list] Toolchain developers: State of GCC HEAD
> IRA will likely cause a lot of spill failures. It has more 
> agressive allocation, so the chance of it running out of base 
> registers is higher.
> The AVR port is fundementally flawed in its handling of 
> reloads around base pointer and frame register.
> (existing bug reports show some examples)
> You should be able to see these easily in test log file (with 
> IRA enabled). 
> Then you could force it to not remove frame pointer and 
> number of failures will decrease as this remove one main cause.
> There may be some other reasons mixed in.
> With IRA disabled (which I thought was default)  it should be 
> no different of course!

The GCC maintainers decided that IRA was to *replace* the existing register 
allocator in 4.4.0. Which means that any back end that has been ported to IRA, 
will now be using IRA, including the AVR. ;-)

So now it's critical that those reloads get fixed...


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