[Bug binutils/21056] New: tic6x - erroneous disassembly of parallel instructions

[alexis.deruelle at gmail dot com]

https://sourceware.org/bugzilla/show_bug.cgi?id=21056

            Bug ID: 21056
           Summary: tic6x - erroneous disassembly of parallel instructions
           Product: binutils
           Version: unspecified
            Status: UNCONFIRMED
          Severity: normal
          Priority: P2
         Component: binutils
          Assignee: unassigned at sourceware dot org
          Reporter: alexis.deruelle at gmail dot com
  Target Milestone: ---

Created attachment 9755
  --> https://sourceware.org/bugzilla/attachment.cgi?id=9755&action=edit
Patch and test case

Problem : missing or erroneously marked parallel instruction in disassembly
output.

Instructions can be scheduled in parallel.

Consecutive parallel instructions are called an « execution packet ».

If an instruction has it's parallel bit (p-bit) set, the next instruction
belongs to the same execute packet, denoted by a leading '||'.
The last instruction of an execute packet is the first one with
it's p-bit set to 0.

To correctly display the leading '||', it's necessary to
fetch the previous instruction in order to read the p-bit
value.

Execute packets can cross fetch packet boundary leading to 3 cases :

1/ Fetch packet 1 (FP1) is not header based (i.e. all 32 bit instructions) :

FP1+20  :
FP1+24  word#6          INS1
FP1+28  word#7  ||      INS2
------------------------
FP2+0   word#0  ||      INS3
:

Instruction INS3 is displayed as parallel if bit 0 of FP1/word#7 is set.

2/ FP1 is header based and word #6 contains two 16 bit instructions.

FP1+20  :
FP1+24  LSB(word#6)             INS1
FP1+26  MSB(word#6)     ||      INS2
FP1+28  <packet header/word#7>
------------------------
FP2+0   word#0          ||      INS3
:

Instruction INS3 is displayed as parallel if header's p-bit #13
is set (parallel bit of 16 bits instructions are stored in the header).

3/ FP1 is header based but word #6 contains a single 32 bit instruction

FP1+20  :
FP1+24  word#6          INS1
FP1+28  <packet header/word#7>
------------------------
FP2+0   word#0  ||      INS2
:

Instruction INS2 is displayed as parallel if bit 0 of word #6 (p-bit) is set.

Cases 1 & 2 are handled correctly while case 3 isn't (defaulted to
case 2), leading to missing or erroneously marked parallel instruction
in disassembly output.

Patch with test-case attached

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