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Re: [Discuss-gnuradio] Block diagram of FPGA interface
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From: |
Matt Ettus |
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Subject: |
Re: [Discuss-gnuradio] Block diagram of FPGA interface |
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Date: |
Mon, 18 Apr 2005 15:50:07 -0700 |
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User-agent: |
Internet Messaging Program (IMP) 4.0-cvs |
Quoting Achilleas Anastasopoulos <address@hidden>:
> Dear all,
>
> I am trying to understand exactly what kind of SP
> is going on the Rx and Tx path of the FPGA and basic
> Rx/Tx.
>
> I am attaching an eps file (and an xfig file) with a hypothesized block
> diagram that is the result of all the information I have
> collected on the website and the discussions.
>
> Can you comment on that and tell me if this is
> exactly what is going on?
You have the receive path exactly correct. The DACs in the TX path are 128
MS/s, and some of the processing you show happens in a slightly different way,
but the end result is the same.
Matt