[Discuss-gnuradio] 8 bit usrp samples (My first verilog code)

[Martin Dvh]

Hi,
I wanted to be able to get 8 bit samples from the usrp so I tried to hack this 
into the verilog code.

Since I don't want to fry my board I didn't compile and try to install it but 
first want to ask if I am on the right track.
(I didn't even install Quartus II web-edition yet since I am working on linux right now and I could only download a windows version. Is there a 
linux version?)

What I tried to do is using a bit of the FR_MODE register to set the usrp in 
trunc_to_8bit mode.
In that mode it puts the high 8 bits of two channels into one output word.
I don't know if the timing should also be changed somewhere.

Please have a look at it.
(it is a diff against current cvs of the usrp code)

Greetings,
Martin

? bootstrap-mdvh-debian
? usrp-build
? fpga/fpga_8bit.diff
Index: firmware/include/fpga_regs_common.h
===================================================================
RCS file: /cvsroot/opensdr/usrp/firmware/include/fpga_regs_common.h,v
retrieving revision 1.5
diff -u -b -B -r1.5 fpga_regs_common.h
--- firmware/include/fpga_regs_common.h 20 Jul 2005 16:46:07 -0000      1.5
+++ firmware/include/fpga_regs_common.h 17 Aug 2005 23:27:05 -0000
@@ -66,6 +66,7 @@
 #  define  bmFR_MODE_NORMAL                  0
 #  define  bmFR_MODE_LOOPBACK          (1 << 0)        // enable digital 
loopback
 #  define  bmFR_MODE_RX_COUNTING       (1 << 1)        // Rx is counting
+#  define  bmFR_MODE_TRUNC_TO_8BIT     (1 << 2)        // Rx is truncated to 
most significant 8 bits
 
 
 // If the corresponding bit is set, internal FPGA debug circuitry
Index: fpga/sdr_lib/rx_buffer.v
===================================================================
RCS file: /cvsroot/opensdr/usrp/fpga/sdr_lib/rx_buffer.v,v
retrieving revision 1.19
diff -u -b -B -r1.19 rx_buffer.v
--- fpga/sdr_lib/rx_buffer.v    14 Aug 2004 22:33:36 -0000      1.19
+++ fpga/sdr_lib/rx_buffer.v    17 Aug 2005 23:27:05 -0000
@@ -43,6 +43,7 @@
     input rxclk,
     input rxstrobe,
     input clear_status,
+    input trunc_to_8bit,
     output [15:0] debugbus
     );
 
@@ -78,12 +79,36 @@
        store_next <= #1 4'd0;
      else if(rxstrobe & (store_next == 0))
        store_next <= #1 4'd1;
-     else if(~rx_full & (store_next == channels))
+     else if(~rx_full & (store_next == channels)) //This works only for the 8 
bit case if the number of channels is even
        store_next <= #1 4'd0;
      else if(~rx_full & (store_next != 0))
+       if(trunc_to_8bit)
+         store_next <= #1 store_next + 4'd2;
+       else
        store_next <= #1 store_next + 4'd1;
 
    always @*
+     if(trunc_to_8bit)
+       case(store_next)
+         4'd1 : begin
+                  fifodata[7:0] = ch_0[15:11];
+                  fifodata[15:11] = ch_1[15:11];
+                end                  
+         4'd3 : begin
+                  fifodata[7:0] = ch_2[15:11];
+                  fifodata[15:11] = ch_3[15:11];
+                end
+         4'd5 : begin
+                  fifodata[7:0] = ch_4[15:11];
+                  fifodata[15:11] = ch_5[15:11];
+                end
+         4'd7 : begin
+                  fifodata[7:0] = ch_6[15:11];
+                  fifodata[15:11] = ch_7[15:11];
+                end
+         default : fifodata = 16'hFFFF;
+       endcase // case(store_next)     
+     else //if(trunc_to_8bit)
      case(store_next)
        4'd1 : fifodata = ch_0;
        4'd2 : fifodata = ch_1;
Index: fpga/toplevel/usrp_std/usrp_std.v
===================================================================
RCS file: /cvsroot/opensdr/usrp/fpga/toplevel/usrp_std/usrp_std.v,v
retrieving revision 1.14
diff -u -b -B -r1.14 usrp_std.v
--- fpga/toplevel/usrp_std/usrp_std.v   20 Jul 2005 21:41:40 -0000      1.14
+++ fpga/toplevel/usrp_std/usrp_std.v   17 Aug 2005 23:27:05 -0000
@@ -197,6 +197,7 @@
    
    wire loopback = settings[0];
    wire counter = settings[1];
+   wire trunc_to_8bit = settings[2];
 
    always @(posedge clk64)
      if(rx_dsp_reset)
@@ -241,6 +242,7 @@
        .ch_6(ch6rx),.ch_7(ch7rx),
        .rxclk(clk64),.rxstrobe(strobe_decim),
        .clear_status(clear_status),
+       .trunc_to_8bit(trunc_to_8bit),
        .debugbus(rx_debugbus) );
    
    rx_chain #(`FR_RX_FREQ_0,`FR_RX_PHASE_0) rx_chain_0
Index: host/lib/usrp_standard.h
===================================================================
RCS file: /cvsroot/opensdr/usrp/host/lib/usrp_standard.h,v
retrieving revision 1.14
diff -u -b -B -r1.14 usrp_standard.h
--- host/lib/usrp_standard.h    20 Jul 2005 05:34:26 -0000      1.14
+++ host/lib/usrp_standard.h    17 Aug 2005 23:27:06 -0000
@@ -57,7 +57,8 @@
   enum {
     FPGA_MODE_NORMAL     = 0x00,
     FPGA_MODE_LOOPBACK   = 0x01,
-    FPGA_MODE_COUNTING   = 0x02
+    FPGA_MODE_COUNTING   = 0x02,
+    FPGA_MODE_TRUNC_TO_8BIT   = 0x04
   };
 
   ~usrp_standard_rx ();