Re: [Discuss-gnuradio] Regenerating FPGA bit file (USRP-0.9)

[Angilberto Muniz Sb]

Right to the point ! -- thanks Martin.

Angilberto.

--- Martin Dvh <address@hidden> wrote:

> Angilberto Muniz Sb wrote:
> > Do I need any special (not provided) file or
> config to
> > regenerate .rbf files? (2.6 tarball - usp-0.9)
> > 
> > When I open the project file and try to compile
> it, I
> > get a number of errors and warning msgs...
> > 
> > Out of curiosity: the project file makes reference
> to
> > a 'adc_interface.v' file that is non-existent --
> is
> > that right?
> There are still references to a few new files
> missing from usrp/fpga/Makefile.am
> This prevents make dist from putting these files in
> the source-tarball
> So you are missing them.
> Unfortunately make distcheck does not detect these
> errors because the fpga-firmware is not built during
> the normal build process.
> 
> The following patch will resolve the issue in the
> cvs code so a new tarball can be generated with make
> dist.
> In the meantime you can get the missing files by
> checking out the anonymous-cvs code.
> http://sourceforge.net/cvs/?group_id=22397
> Or by manually downloading the files from web-cvs
>
http://cvs.sourceforge.net/viewcvs.py/opensdr/usrp/fpga/sdr_lib/
> 
> The missing files are:
> sdr_lib/adc_interface.v
> sdr_lib/bidir_reg.v
> sdr_lib/hb/acc.v
> sdr_lib/hb/coeff_rom.v
> sdr_lib/hb/halfband_decim.v
> sdr_lib/hb/mult.v
> sdr_lib/hb/ram16_2port.v
> sdr_lib/hb/ram16_2sum.v
> sdr_lib/hb/ram32_2sum.v
> sdr_lib/hb/hbd_tb/test_hbd.v
> sdr_lib/hb/hbd_tb/run_hbd
> sdr_lib/hb/hbd_tb/HBD
> sdr_lib/io_pins.v
> sdr_lib/rx_chain_hb.v
> sdr_lib/rx_dcoffset.v
> sdr_lib/setting_reg.v
> 
> Greetings,
> Martin
> 
> > 
> > Thank you,
> > 
> > Angilberto.
> > PS: If I try the same thing on usrp-0.8 everything
> > goes ok -- 100% compile, no errors.
> > 
> > 
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>
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> > 
> 
> > Index: fpga/Makefile.am
>
===================================================================
> RCS file: /cvsroot/opensdr/usrp/fpga/Makefile.am,v
> retrieving revision 1.3
> diff -u -r1.3 Makefile.am
> --- fpga/Makefile.am  20 Nov 2005 06:39:25 -0000      1.3
> +++ fpga/Makefile.am  13 Dec 2005 02:39:42 -0000
> @@ -79,6 +79,8 @@
>       models/fifo_4k.v                \
>       models/pll.v                    \
>       models/ssram.v                  \
> +     sdr_lib/adc_interface.v         \
> +     sdr_lib/bidir_reg.v             \
>       sdr_lib/bus_interface.v         \
>       sdr_lib/cic_decim.v             \
>       sdr_lib/cic_int_shifter.v       \
> @@ -92,17 +94,30 @@
>       sdr_lib/ext_fifo.v              \
>       sdr_lib/gen_cordic_consts.py    \
>       sdr_lib/gen_sync.v              \
> -     sdr_lib/hb                      \
> +     sdr_lib/hb/acc.v                \
>       sdr_lib/hb/coeff_ram.v          \
> -     sdr_lib/hb/halfband_interp.v    \
> +     sdr_lib/hb/coeff_rom.v          \
> +     sdr_lib/hb/halfband_decim.v             \
> +     sdr_lib/hb/halfband_interp.v            \
>       sdr_lib/hb/mac.v                \
> +     sdr_lib/hb/mult.v               \
>       sdr_lib/hb/ram16.v              \
> -     sdr_lib/master_control.v        \
> +     sdr_lib/hb/ram16_2port.v                \
> +     sdr_lib/hb/ram16_2sum.v         \
> +     sdr_lib/hb/ram32_2sum.v         \
> +     sdr_lib/hb/hbd_tb/test_hbd.v            \
> +     sdr_lib/hb/hbd_tb/run_hbd               \
> +     sdr_lib/hb/hbd_tb/HBD           \ 
> +     sdr_lib/io_pins.v               \
> +     sdr_lib/master_control.v                \
>       sdr_lib/phase_acc.v             \
>       sdr_lib/ram.v                   \
>       sdr_lib/rx_buffer.v             \
>       sdr_lib/rx_chain.v              \
> +     sdr_lib/rx_chain_hb.v           \
>       sdr_lib/rx_chain_dual.v         \
> +     sdr_lib/rx_dcoffset.v           \
> +     sdr_lib/setting_reg.v           \
>       sdr_lib/serial_io.v             \
>       sdr_lib/sign_extend.v           \
>       sdr_lib/strobe_gen.v            \
> 


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