Trond Danielsen wrote:
> after having read several papers on the subject, I am still not able
> to find the answer I am looking for. I wonder how to calculate the
> frequency resolution of the CORDIC algorithm. In an earlier post to
> this mailing list it was stated that the resolution is approximately
> 0.01 Hz. Could anyone point me to where I can find a deviation of
> this result?
The "phase generator" part of the CORDIC block works by incrementing a
32-bit phase register by a fixed amount per clock cycle. The full size
of the register represents 2*PI() of phase, or one cycle of the
waveform. The user programmed phase increment per clock cycle then
represents frequency.
In the receive chain of the FPGA, the phase generator is clocked at 64
MHz. Thus, the minimum delta-frequency (a one bit change in the phase
increment register) is 64 MHz / pow(2, 32) = 0.0149 Hz.
Thus, for DC, the phase increment value is zero, for 0.0149 Hz, it is 1,
for 0.0298 Hz, it is 2, all the way up to 32 MHz, where it is pow(2,
31). You can also tune negative frequencies, where -1 creates -0.0149
Hz, etc.
The CORDIC block then uses the resulting "sawtooth" phase value to
rotate the incoming signal by that amount, resulting in complex
frequency conversion.
Did this help, or confuse?