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Re: [Discuss-gnuradio] rssi questions

From: George Nychis
Subject: Re: [Discuss-gnuradio] rssi questions
Date: Thu, 16 Aug 2007 13:48:25 -0400
User-agent: Thunderbird (X11/20070604)

Eric, we want feedback from you on this one :)

I think you're right Jonathan, for performing carrier sense in the FPGA, we really do not need it in dB. Calculating the average to determine a threshold will get the job done with less the hassle. And right, if the host really wants it in dB, it can do the conversion.

So here is what I want feedback on... how to communicate the RSSI to the host. What we figure is that the host should determine the threshold, in other words calculate the average and write it to a register that the FPGA can read. This saves the floating point computation on the FPGA, and the host can decide how many RSSI samples it wants to compute the threshold on.

But, we've already determined that the 6-bits in the header are not enough for properly reading the RSSI from the FPGA. So, what do we want to do about this?

We can store the RSSI in a register and read from it using C/S packets, then compute the average. This gives the full 32-bits.

However, I still think it would be useful for each packet to contain an RSSI reading. I'm sure others would put use to this in the future. I propose adding a 32-bit RSSI field to the packet header. This doesn't even incur 1% overhead, it's ~.7% additional overhead per packet. Then with the higher bandwidth of USRP2, it's going to become even more insignificant.

- George

Johnathan Corgan wrote:
George Nychis wrote:

We want to compute the RSSI in dB on the FPGA, we're not even
interested in the FPGA responding back with the RSSI at this point.

Okay, but--why do you need units of dB?  This is in the log domain, so
at some point on the FPGA you'll need to take a logarithm of an
amplitude.  If it is for the user's benefit, then it is much simpler to
do the conversion on the host.

1. What exact information needs to be shared?

The output of the ADC is a fixed multiple of the signal at the antenna
input.  Since the gain settings are controlled by the host, the host
would need to calculate what the overall gain is and poke a register
with a value the FPGA logic could use.

Again, though, why do you need to get the actual RSSI?  If you're going
to use it for carrier-sense, then all you really need to do is threshold
the average magnitude of the ADC output.  You've already got that value
calculated in rssi.v (perhaps that's a confusing name for the Verilog file.)

The only downside of rssi.v output is that the time constant for
averaging is fixed (to make the logic very simple, fast, and low-area.)

2. Where can we get the information? I'm assuming when the daughterboards are initialized most of this information is available.

It would be different for each daughterboard, but code could be added to
the host daughterboard handling code to determine the overall antenna to
ADC gain when the gain settings are set by the user.  That overall gain
value would then be poked into a register on the FPGA to be used by your
code to get actual antenna power (assuming you still really need to do

Finally, for an AGC, the power measurement portion of the control loop
doesn't need to be taken all the way to dB.

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