Re: [Discuss-gnuradio] A Verilog question or two

[Daniel O'Connor]

On Thursday 16 October 2008 01:00:19 Jason Uher wrote:
> 2008/10/14 Daniel O'Connor <address@hidden>:
> > On Wednesday 15 October 2008 01:15:48 Sebastiaan Heunis wrote:
> >> always @(posedge clk)
> >> begin
> >>  tap1 <= #1 input;
> >>  tap2 <= #1 tap1;
> >>  tap3 <= #1 tap2;
> >> end
> >>
> >> the #1 ensures that tap1 gets updated before tap2?
> >
> > According to what I have read with about synthesis tools the delays will
> > be ignored totally.
> >
> > I see a lot of it though, so I don't know if it's superstition or the
> > manual lies.
>
> I think the delays are just for simulation.  In synthesis the
> assignments take a real amount of time to complete (because it's
> hardware).  If you are dependent on that delay, you need to signify
> that in simulation, otherwise the assignment would occur at the same
> simulation timestep as everything else and you could be using new data
> instead of old.  Most likely synthesis ignores them, but they are
> needed for the simulation (I'm not 100% sure, I usually remove all
> such delays before synthesis testing).

Hmm.. I think it's more likely to be superstition for broken simulators then..

A book I have (Kilts - Advanced FPGA design) states that 
"Delays are always ignored by synthesis tools, and this type of modeling can 
easily create mismatches between simulation and synthesis." (page 167).

-- 
Daniel O'Connor software and network engineer
for Genesis Software - http://www.gsoft.com.au
"The nice thing about standards is that there
are so many of them to choose from."
  -- Andrew Tanenbaum
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