You see in the FPGA codec datas are interpolated into 32Msps and sended to AD9862. Then AD9862 interpolates the datas by 4. But AD9862 is configured to latch datas using CLKOUT1,and CLKOUT1 is 64M. Though CLKOUT1 is not linked to FPGA, it seems a little confilcting.
So can anyone tell me the how exactly AD9862 latches datas? Besides,does the 64Msps A/D and 128Msps D/A in the datasheet of AD9862 mean the maximum achievable rates or the fixed working rates? If I change the VCTCXO,for example 40M,then will AD9862 work according to 40M?
The FPGA operates at 64Msps by default, not 32Msps. I agree the clocking is a little confusing, we're not doing true source-synchronous clocking with the AD9862. Instead the FPGA and the AD9862 both share the same clock from the clock distribution chip, which the AD9862 uses internally as CLKOUT1.
The AD9862 can work at lower rates. If you are using a B100 or E100, you can pass the "master_clock_rate" argument to UHD on startup. For instance, to clock the AD9862 and FPGA at 32Msps, you can use:
The D/A rate will be twice the A/D rate; in this example, the D/A operates at 64Msps.