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From: | NaceurElOuni |
Subject: | Re: [Discuss-gnuradio] About "FPGA-ADC/DAC and RF frontend" Latency |
Date: | Fri, 3 May 2013 15:40:33 -0700 (PDT) |
Hint 1: If both 210s are on the same PPS and frequency reference and the FPGA clocks are synchronized to the PPS, you can schedule the transmit and receive to within one tick of the 100 MHz ADC clock.
Hint 2: Cross correlate the transmitted and received samples. The lag will be independent of Ethernet and IP delays.
-Marc
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