Re: [Discuss-gnuradio] About "FPGA-ADC/DAC and RF frontend" Latency

[NaceurElOuni]

Hi Ben,

Thanks for explanations,

I've been doing some theoretical calculations on the group delay estimation and found that this part is giving negligible latency compared to the Ethernet portion between USRP and host.

cheers.

2013/5/3 Naceur Amine El Ouni <[hidden email]>

Thank you Marc,  

* Ok I will try using a common clock ref and input PPS

 

* Scheduling the transmit and receive  to within one tick of the 100 MHz ADC clock: Can that be done into the host GNU radio code or am supposed to move the code to the FPGA.  

* Is that the samples count method to get accurate time-stamping ?

* Can you please explain to me more about the concept of cross correlating transmitted and received samples. 

2013/5/3 mepard [via GnuRadio] <[hidden email]>

Hint 1:  If both 210s are on the same PPS and frequency reference and the FPGA clocks are synchronized to the PPS, you can schedule the transmit and receive to within one tick of the 100 MHz ADC clock.
Hint 2:  Cross correlate the transmitted and received samples. The lag will be independent of Ethernet and IP delays.

-Marc

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Naceur Amine El Ouni, B. Ing

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Naceur Amine El Ouni, B. Ing

Laboratoire LaCIME. 

École de technologie supérieure

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Tel : 514 396-8800, ext. 7608

Cell : 438-868-2240

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