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[Gnucap-devel] Problem with logic elements on transient simulation

From: Rupert Swarbrick
Subject: [Gnucap-devel] Problem with logic elements on transient simulation
Date: Mon, 05 Nov 2012 09:58:14 +0000
User-agent: Gnus/5.130004 (Ma Gnus v0.4) Emacs/22.3 (gnu/linux)

With the following circuit:

  .parameter LOGIC_LEVEL = 5
  .parameter RISE = 10n
  .parameter PERIOD = 50u

  .model cmos LOGIC
  * A simple S/R latch
  .subckt flipflop q vdd s r
  U1 q 0 vdd vdd 3 qbar cmos NAND
  U2 qbar 0 vdd vdd 4 q cmos NAND
  U3 3 0 vdd vdd s cmos INV
  U4 4 0 vdd vdd r cmos INV
  .ends flipflop

  VDD (vdd 0) dc LOGIC_LEVEL
  XSR (q vdd vclk 0) flipflop

  .print tran v(nodes) 
  .tran 0 100u 1e-3 trace all >pwr.log

I get the expected complaints about not having an analogue subckt model
(fine), but also get two lines


Hunting through the code, I think I've worked out what's going
on. Switching on tracing (and commenting out bit-rotted lines so it
would compile, grrr), I saw that this is caused when VCLK first goes
high. This is attached to the S line of the SR latch and causes the
various states to be recomputed. The new output of U1 becomes TRUE (this
is "Q"), and the new output of U2 will become false. Unfortunately, the
response U2 is computed before U1 for whatever reason. This would be
fine, but the result is that U2 ends up with an indeterminate output
again in

This triggers the unreachable() call or, if you compile with
--enable_debug, it triggers the assertion just beforehand.

The resulting trace in log.txt is junk, but I haven't carefully traced
out what's causing this. I've attached it to this message, in case it's


(1) Is this a bug? (I presume so, but thought I should check!)

(2) Has anyone written down an explanation of how d_logic should work
    somewhere? I'd happily search for a fix, but it feels like I'm
    stumbling around in the dark a little bit.

(3) Is this going to be irrelevant if/when upcoming VHDL/Verilog work
    gets merged?

Not quite on the same topic:

(4) Is there an "official" development repository? I am using
    git://, but this is just imports of
    various snapshots. And the most recent non-git-related change is
    from 2009(!)

Many thanks for any help,


#Time       v(q)       v(vclk)    v(vdd)    
 0.         2.5        0.         5.        
 10.E-6     2.5        0.         5.        
 20.E-6     2.5        0.         5.        
 30.E-6     2.5        0.         5.        
 40.E-6     2.5        0.         5.        
 50.E-6     2.5        0.         5.        
 50.01E-6   2.5        5.         5.        
 50.011E-6  0.         5.         5.        
 50.012E-6  5.         5.         5.        
 50.013E-6  5.         5.         5.        
 50.019E-6  5.         5.         5.        
 50.31E-6   5.         5.         5.        
 50.32E-6   5.         1.552E-12  5.        
 50.32E-6   2.5        0.         5.        
 50.321E-6  2.5        0.         5.        
 50.321E-6  2.5        0.         5.        
 50.321E-6  2.5        0.         5.        
 50.326E-6  2.5        0.         5.        
 51.62E-6   2.5        0.         5.        
 63.185E-6  2.5        0.         5.        
 100.E-6    2.5        0.         5.        

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