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Re: [Patch] [bug #26237] multiple problems with usb devices

From: Vladimir 'φ-coder/phcoder' Serbinenko
Subject: Re: [Patch] [bug #26237] multiple problems with usb devices
Date: Sun, 23 May 2010 21:35:54 +0200
User-agent: Mozilla-Thunderbird (X11/20091109)

>  =20
>> Ale=C5=A1 Nesrsta wrote:
>>    =20
>>> I will look into yeeloongfw branch, I got Bazaar working yesterday
>>> evening only... I agree with You, first should be solved known proble=
>>> on simple base.
>>> Unfortunately, I probably cannot help You as I don't have GEODE or
>>> Yeeloong... I can hope only that my corrections would help You or
>>> inspire You in some other ways.
>>> For me were very "disgusting", unexpected and hard to find problems w=
>>> short max. packet size on control pipe and problem with toggling bulk=

>>> transfers when EP have numbers 0x01 and 0x81.
>>>  =20
>>>      =20
>> Forgot to mention: on Yeeloong the value you write into  registers
>> expecting the memory address is not the same as the value of the point=
>> so simple cast won't work. You need to use dma32_alloc, dma_get_virt a=
>> dma_get_phys functions.
>>    =20
> Hi,
> it is interesting - why on Yeeloong only ? Why it is not needed on
> "normal" GRUB ?
>  =20
There are multiple considerations:
1) PCI BARs on Yeeloong don't map into standard address space but in
separate windows found at 0xb0000000.
2) In kernel mode memory starts from 0x80000000 and not 0 as on x86 in
no-paging mode.
3) But if you want to circumvent cache you need to OR 0x20000000 to your
4) PCI DMA space starts from 0x80000000
So if you allocate e.g. 0x81234560 then you have to write 0x81234560 to
registers but use 0xa1234560 in pointer.
On some platforms like sparc and PPC grub has to work in an environment
where mapping is even more difficult.
> And another idea - could be there some problem with PCI memory mapped
> register access caching ? Some Linux drivers uses so called "barrier"
> when doing access to PCI memory to be sure that previous access was
> really done - could be there such case ?
>  =20
I'm not sure. I've looked into intel manual and it looks like it
supposes mobo has some kind of way to inform CPU of memory writes/reads.
This may be wrong impression from very fast look into spec.
Also there are MTRR and cacheability attribute in page table.
> Best regards
> Ales
> _______________________________________________
> Grub-devel mailing list
> address@hidden
>  =20

Vladimir '=CF=86-coder/phcoder' Serbinenko

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