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[Help-gnucap] Time step control

From: a r
Subject: [Help-gnucap] Time step control
Date: Sat, 1 Dec 2007 17:17:52 +0000

I think default settings for the time-step control are too aggressive.

I am getting best results with the following settings:

.option method=euler dtmin=1e-16 reltol=1e-4 itl3=3 itl4=4

.tran 1n 20n trace alltime > inverter_test.dat

If I do not specify low thresholds for itl3, itl4 gnucap has a
tendency to use maximum allowed time steps (here 1n) and "jump over"
all interesting transistions.

The test circuit is attached. Note that without setting itl3, itl4 the
results are not readable (although they might be considered

If the time step is set to 0.001 (and itl3, itl4 are not set) the
output is good but the time step is effectively constant which is not
good for simulating sampled circuits.

The question is: are the defaults sensible?

* inverter test

.include TSMC_025u_Mosis.txt

.subckt inv vdd vss out in
Mp out in vdd vdd CMOSP l=0.25u w=1.5u
Mn out in vss vss CMOSN l=0.25u w=0.9u
.ends inv

.parameter p_vdd=2.5

vvdd vdd vss 'p_vdd'
vvss vss 0 0

vck in vss pulse (0 'p_vdd' 2.5n 0.01n 0.01n 1.48n 4.5n)

xi1 vdd vss n1 in inv
xi2 vdd vss n2 n1 inv
xi3 vdd vss n3 n2 inv
xi4 vdd vss n4 n3 inv

.option acct
.option method=euler dtmin=1e-16 reltol=1e-4 itl3=3 itl4=4
*.option method=euler dtmin=1e-16 reltol=1e-4

.probe tran v(nodes)


.tran 1n 20n trace alltime >inv_test.dat
*.tran 0.001n 20n trace alltime >inv_test.dat



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