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Re: [Help-gnucap] Bug? convergence problem?

From: al davis
Subject: Re: [Help-gnucap] Bug? convergence problem?
Date: Mon, 21 Feb 2011 10:22:21 -0500
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On Thursday 10 February 2011, Orestes Mas wrote:
> I'm facing a weird result when I simulate a simple inverter
> amplifier built  around an operational amplifier. Basically
> I'm trying to obtain the input- output transfer
> characteristic (for educational purposes), but if the number
> of points in the DC command is low, I obtain an spurious
> peak at the output.

As Gena said, tighten the tolerance.

In this case, a macro model, only a few components are checked 
for convergence.  With an all-transistor model of an op-amp, the 
output transistors would be checked for convergence, which would 
usually force more iterations even though the input difference 
is small.  In this model, the output section is linear, with no 
convergence checking.

The input transistors are checked, but voltage and current are 
small, so it is easy for errors to slip by.  Gena said to 
tighten abstol.  This is good advice.  It might be a good idea 
to also tighten vntol.

The changes you made to the model, replacing "poly" devices with 
a multi-element equivalent, is not as equivalent as it might 
look.  The "poly" elements are checked for convergence.  The 
linear replacements are not.

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