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Jose Maria Rodriguez Millan
Wed, 7 Feb 2001 02:28:29 +0100
Please,can you help me with this doubt about makefile?
I've the following scenario:
Have a group of targets (libs), each one in a separate directory,say
The commands to make all them are the same;not so the
prerrequisites,but they can be computed from the
target names,but just in case $(@D) is already defined by makefile
when expanding the prerrequisites.
For example,if each lib directory has a src subdirectory
(a/src,b/src,c/src) ,i can get the list of prerrequisites
$(subst .cc,.o,$(wildcard $(addsuffix /src/*.cc,$(@D))))
but this expression seems not to work if written as prerrequisite (i
suppose because $(@D) is defined only when
command execution begins.If it were so ,would not be interesting to have
target-related variables already defined
when computing prerrequisites?))
In the end,what i want to do is:
$(PROJECTLIBS) : <calculate prerrequisites,based in current target path>
Is this possible?Is there any other way to do the same thing?
Thanks for your help and time,
- (no subject),
Jose Maria Rodriguez Millan <=