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Wed, 13 Apr 2005 07:43:35 +0000
I was wondering if there is an option to get the expanded version of a
Makefile as when you get expansion of macros with gcc -E ?
For example, if my Makefile is:
gcc -c -o $(OBJ) $(SRC)
"make -E" would print:
gcc -c -o foo.o foo.c
I've tried 'make -p' and 'make -d', but none of them are actually giving me
the output I am looking for. Is there any solution?
- make expansion?,
Sebastien Mirolo <=