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Re: Need support regarding the execution order of GNU Make rules

From: Christian Hujer
Subject: Re: Need support regarding the execution order of GNU Make rules
Date: Wed, 1 Apr 2015 10:14:40 +0530


The dependency files are gendered first most likely because they are
included with a statement like
-include $(sources_c:.c=.d)

By the way, to me or doesn't make sense to make the object file dependent
on the dependency file.

 On Apr 1, 2015 10:05 AM, "Basil Mathew" <address@hidden> wrote:

> Dear Support,
> My name is Basil Mathew. I work as a support engineer, for a Windows
> Eclipse based build platform that uses GNU Make scripts, in my
> organization. I have been asked to take over the GNU Make script support
> and maintenance for the future. I was going through our GNU Make scripts
> for build with the help of the GNU Make Manual and the book “Managing
> Projects With Gnu Make” for the last week and half. It has been difficult,
> but I am slowly making progress.
> I have a question(not related to implementation, but more related to why it
> happens the way it happens) for which I have not been able to find a
> suitable explanation neither in the manual nor over the internet. Would it
> be possible for some one to have a look into this question and help me out?
> I would really appreciate the help.
> *Version Info:*
> Running "gmake -version" at the command prompt gives me this output.
> C:\>gmake -version
> GNU Make 3.80
> Copyright (C) 2002  Free Software Foundation, Inc.
> This is free software; see the source for copying conditions.
> There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A
> The cpp.exe version that we are using as of now is "GNU CPP version
> egcs-2.91.57 19980901 (egcs-1.1 release) (80386, BSD syntax)"
> *Build Environment Basics:*
> In our build environment, the compilation of a C-file into the object file
> is a 2 step process as described below. We use the GNU’s “cpp.exe” to
> generate the dependency file and then compile the C source file using the
> specific compiler that is configured for the project. We have 2 separate
> make rules to get this done.
> We generate the list of object files to be created as mentioned below
> sources_c = $(filter %.c,$(GEN_FILE_C))
> objects_c = $(sources_c:.c=.o)
> where the variable “GEN_FILE_C” will contain the list of input C source
> files. A project usually contains more than 30 C Source files.
> The rule for compilation is defined as
> build_c: $(objects_c)
> %.o: %.c %.d
>     !!!!Execute the Compiler Call to create the object file
> The rule for dependency generation is defined as
> %.d: %.c
>     !!!!Execute the cpp.exe call to generate the dependency file
> We invoke the make rule “build_c”. Also we invoke the makefile with the
> “-j” option that takes “ENV{NUMBER_OF_PROCESSORS}” as the argument.
> *Question:*
> I find that the build works fine, no problem with the build.
> Only problem that I have is that I cannot explain why the dependencies
> generation phase for all the 30 or more C source files are executed first
> completely before the compilation commands for any C-source files are
> executed.
> I was assuming that the dependency generation for one C-source file will be
> completed followed by the compilation commands for the particular C-source
> file followed by the dependency generation for next C-source file and so
> on.
> Can you please explain the reason behind this if you are aware of this?
> Thanks & Regards
> Basil Mathew.
> _______________________________________________
> Help-make mailing list
> address@hidden

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