Re: DOCS: include a sample "Makefile"?

[Jonathan Kulp]

Werner LEMBERG wrote:
> > parts:
> >         $(LILY_CMD) $(wildcard Parts/*.ly)
> >         mv *.pdf $(OUTDIR)/
>
> `wildcard' is a GNU extension.  It can be circumvented with shell
> commands, however, I suggest to name the part files explicitly.

Pity.  In that case, the original approach is best for portability I 
suppose.  Here's how I have the "parts" target now:

parts:
        for LILYFILE in Parts/*.ly ; do $(LILY_CMD) "$$LILYFILE" ; done
        mv *.pdf $(OUTDIR)/

It works exactly as it did with the GNU wildcard, except that multiple 
files can't be compiled at once with separate processors.  I'll probably 
stick with the GNU wildcard approach in my personal makefiles, or else 
have both lines in there with one commented out.

> > > $(OUTDIR)/%.pdf: Scores/%.ly
>
> Percent rules are a GNU extension.
>
> > > define movement_pdf_target
>
> Macro definitions are a GNU extension.
>
> > > $(foreach m, MOVEMENTS, $(call movement_pdf_target,$(m))
>
> Both `foreach' and `call' are GNU extensions.

This won't affect my Makefiles since I didn't understand this stuff 
anyway. :)

Thanks Werner,

Jon
--
Jonathan Kulp
http://www.jonathankulp.com