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Re: [lwip-users] Low Iperf performance of lwip 1.4.1 on STM32 and FreeRT

From: Claudius Zingerli
Subject: Re: [lwip-users] Low Iperf performance of lwip 1.4.1 on STM32 and FreeRTOS
Date: Mon, 01 Jul 2013 09:56:08 +0200
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Hi ella and all,

Some progress here: I receive a lot of CRC & Align errors (MMC counters of STM32). At least there is /some/ correlation between these errors and LWIP behaving strangely (if there is an increase in the MMC counters, LwIP gets into trouble, if there is none, LwIP mostly works fine). This may further be related to the usage of RMII between the MAC and PHY and creating the RMII-Clock with the STM32-PLL. Datasheet jitter and precision should be OK for the PHY, but this might not be the cleanest solution (There is some hint in the datasheet that good guys should source the RMII clock by bypassing the PLL). So in a next step, I'm going to use a dedicated 50MHz oscillator to clock the PHY and MCU. On the software-side: An own implementation of the MAC driver is on the way. Could probably be open sourced if there is some interest.


On 6/23/2013 7:16 AM, ella wrote:
The problem is not FreeRTOS but buggy and ugly STM32 netif driver. I have
studied original driver provided by ST and had nothing but rewrite it.

Just one example of wrong architecture of this driver. This is from

     buffer =  (u8 *)(DMATxDescToSet->Buffer1Addr);
     for(q = p; q != NULL; q = q->next)
       memcpy((u8_t*)&buffer[l], q->payload, q->len);
       l = l + q->len;

Consider that buffers are allocated as
extern uint8_t Tx_Buff[ETH_TXBUFNB][ETH_TX_BUF_SIZE];
and are linked to chained DMA descriptors.

If packet size bigger then ETH_TX_BUF_SIZE you are at potential danger of
wrap around that is not treated in code. Same happens for RX flow. So no
surprise you have a problems with big packets.
And this is only one place, there is a number of others. There are also a
few races.

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