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Re: [lwip-users] Low Iperf performance of lwip 1.4.1 on STM32 and FreeRT

From: Claudius Zingerli
Subject: Re: [lwip-users] Low Iperf performance of lwip 1.4.1 on STM32 and FreeRTOS
Date: Tue, 02 Jul 2013 13:50:20 +0200
User-agent: Mozilla/5.0 (Windows NT 5.1; rv:17.0) Gecko/20130620 Thunderbird/17.0.7

On 7/1/2013 9:00 PM, Jeff Barlow wrote:
On 7/1/2013 12:56 AM, Claudius Zingerli wrote:
[RMII-Clock from PLL is bad]
This is a known issue. Deriving the RMII-Clock with the STM32-PLL is
just not a robust design.

There are several PHY chips (Micrel, etc) that have built in RMII clock
generators that can use a low cost 25MHz crystal and provide a nice low
jitter clock back to the MCU.

In the final design, we plan use a 3-port switch from Micrel. It can be clocked from 25MHz or 50MHz, but the board I'm using to develop the software has a DP83848 that does need a 50MHz clock source for RMII. STM32F4 /might/ be able to handle 50MHz as a main clock source. (The datasheet is ambiguous about that: The drawing says 4-26MHz HSE, but the table says 1-50MHz HSE. One could interpret that as from 26MHz one has to use an oscillator, below an Xtal would fit as well)



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