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Re: [Qemu-arm] [PATCH v2 1/2] target-arm: Fix handling of SDCR for 32-bi

From: Peter Maydell
Subject: Re: [Qemu-arm] [PATCH v2 1/2] target-arm: Fix handling of SDCR for 32-bit code
Date: Fri, 19 Feb 2016 16:38:34 +0000

On 19 February 2016 at 16:31, Sergey Fedorov <address@hidden> wrote:
> On 19.02.2016 17:39, Peter Maydell wrote:
>> +static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
>> +                       uint64_t value)
>> +{
>> +    env->cp15.mdcr_el3 = value & SDCR_VALID_MASK;
>> +}
>> +
> Just one comment. As soon as we cannot have both of MDCR_EL3 in SDCR in
> a specific CPU configuration (EL3 is either AArch64 or AArch32), the
> RES0 bitfields of SDCR are "RES0 in all contexts". Thus we can choose
> "The bit is hardwired to 0" behaviour as we do here. We could also
> choose another behaviour "The bit can be written" and check for "EL3 is
> AArch64" case before trying to interpret those bits.

Yes, as you say we could do either (and we have examples of both in
QEMU currently, as well as examples of "we don't do either and if
the guest writes in a bit it should not it will get a feature it
shouldn't in theory have"). Masking on write seemed simpler here.

-- PMM

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