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Re: [Qemu-arm] [Qemu-devel] [PATCH v4 09/14] pci: Add support for Design

From: Marcel Apfelbaum
Subject: Re: [Qemu-arm] [Qemu-devel] [PATCH v4 09/14] pci: Add support for Designware IP block
Date: Wed, 17 Jan 2018 18:17:27 +0200
User-agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.13; rv:52.0) Gecko/20100101 Thunderbird/52.4.0

On 17/01/2018 18:12, Andrey Smirnov wrote:
On Wed, Jan 17, 2018 at 7:23 AM, Marcel Apfelbaum
<address@hidden> wrote:

Hi Peter,

On 16/01/2018 16:34, Peter Maydell wrote:

On 16 January 2018 at 01:37, Andrey Smirnov <address@hidden>

Add code needed to get a functional PCI subsytem when using in
conjunction with upstream Linux guest (4.13+). Tested to work against
"e1000e" (network adapter, using MSI interrupts) as well as
"usb-ehci" (USB controller, using legacy PCI interrupts).

Cc: Peter Maydell <address@hidden>
Cc: Jason Wang <address@hidden>
Cc: Philippe Mathieu-Daudé <address@hidden>
Cc: address@hidden
Cc: address@hidden
Cc: address@hidden
Signed-off-by: Andrey Smirnov <address@hidden>
   default-configs/arm-softmmu.mak  |   2 +
   hw/pci-host/Makefile.objs        |   2 +
   hw/pci-host/designware.c         | 618
   include/hw/pci-host/designware.h |  93 ++++++
   include/hw/pci/pci_ids.h         |   2 +
   5 files changed, 717 insertions(+)
   create mode 100644 hw/pci-host/designware.c
   create mode 100644 include/hw/pci-host/designware.h

I'm not familiar enough with our PCI code to be able to review
this, I'm afraid. MST and Marcel are our PCI subsystem maintainers --
could one of you have a look at whether this seems to be a correct
implementation of a pcie host controller ?

Sadly PCI Host bridges do not have a standard, each HW vendor
can do pretty much what they want.

That being said, if Andrey can point me to the PCI spec for the Designware
PCI host bridge and what parts they implemented for it I can have a look,
(I will not be available for a week or so, but right after)

Just in case you still want this:

To the best of my knowledge, Synposys does not provide specification
for their PCIe IP to general public and I am in no way affiliated with
them, so I don't have any backchannels to get it any other way.

The next best thing to an actual spec, that I found to be pretty
useful, is PCIe chapter of i.MX6Q Reference Manual
(https://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf   page
4049), which is what I used to implement the code in question.


Last, and probably the most important, "source of truth" was actual
Linux PCIe driver for i.MX/Designware which I used as a sort of
inverse reference implementation.

We did the same for our PVRDMA device implementation :)


Andrey Smirnov

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