|
From: | Jae Hyun Yoo |
Subject: | Re: [PATCH 4/5] aspeed/i2c: Add support for DMA transfers |
Date: | Wed, 16 Oct 2019 12:03:58 -0700 |
User-agent: | Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 |
On 10/16/2019 1:50 AM, Cédric Le Goater wrote:
The I2C controller of the Aspeed AST2500 and AST2600 SoCs supports DMA transfers to and from DRAM. A pair of registers defines the buffer address and the length of the DMA transfer. The address should be aligned on 4 bytes and the maximum length should not exceed 4K. The receive or transmit DMA transfer can then be initiated with specific bits in the Command/Status register of the controller. Signed-off-by: Cédric Le Goater <address@hidden>
Tested-by: Jae Hyun Yoo <address@hidden>
[Prev in Thread] | Current Thread | [Next in Thread] |