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Re: [RESEND RFC PATCH v2 1/2] target/arm: Allow to inject SError interru

From: Gavin Shan
Subject: Re: [RESEND RFC PATCH v2 1/2] target/arm: Allow to inject SError interrupt
Date: Fri, 14 Feb 2020 13:25:13 +1100
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.2.0

On 2/13/20 9:31 PM, Peter Maydell wrote:
On Thu, 13 Feb 2020 at 03:49, Gavin Shan <address@hidden> wrote:
On 2/12/20 10:34 PM, Peter Maydell wrote:
Yeah, this is on my list to look at; Richard Henderson also could
have a look at it. From a quick scan I suspect you may be missing
handling for AArch32.

Yes, the functionality is only supported on aarch64 currently by intention
because the next patch enables it on "max" and "host" CPU models and both
of them are running in aarch64 mode.


If you really want to get this supported for aarch32 either, I can do
it. However, it seems there is a long list of aarch32 CPU models, defined
in target/arm/cpu.c::arm_cpus. so which CPU models you prefer to see with
this supported? I think we might choose one or two popular CPU models if
you agree.

I don't think you should need to care about the CPU models.
We should implement SError (aka "asynchronous external
abort" in ARMv7 and earlier) generically for all CPUs. The
SError/async abort should be triggered by a qemu_irq line
inbound to the CPU (similar to FIQ and IRQ); the board can
choose to wire that up to something, or not, as it likes.

Yes, what I need to care about is board with this. It means
I will get this supported on "virt" only. Thanks for the comments
and the changes will be included in v3.


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