[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH 02/41] hw/intc/arm_gicv3: Sanity-check num-cpu property
From: |
Peter Maydell |
Subject: |
[PATCH 02/41] hw/intc/arm_gicv3: Sanity-check num-cpu property |
Date: |
Fri, 8 Apr 2022 15:15:11 +0100 |
In the GICv3 code we implicitly rely on there being at least one CPU
and thus at least one redistributor and CPU interface. Sanity-check
that the property the board code sets is not zero.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
Doing this would be a board code error, but we might as well
get a clean diagnostic for it and not have to think about
num_cpu == 0 as a special case later.
---
hw/intc/arm_gicv3_common.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
index 4ca5ae9bc56..90204be25b6 100644
--- a/hw/intc/arm_gicv3_common.c
+++ b/hw/intc/arm_gicv3_common.c
@@ -328,6 +328,10 @@ static void arm_gicv3_common_realize(DeviceState *dev,
Error **errp)
s->num_irq, GIC_INTERNAL);
return;
}
+ if (s->num_cpu == 0) {
+ error_setg(errp, "num-cpu must be at least 1");
+ return;
+ }
/* ITLinesNumber is represented as (N / 32) - 1, so this is an
* implementation imposed restriction, not an architectural one,
--
2.25.1
- [PATCH 00/41] arm: Implement GICv4, Peter Maydell, 2022/04/08
- [PATCH 02/41] hw/intc/arm_gicv3: Sanity-check num-cpu property,
Peter Maydell <=
- [PATCH 05/41] target/arm/cpu.c: ignore VIRQ and VFIQ if no EL2, Peter Maydell, 2022/04/08
- [PATCH 03/41] hw/intc/arm_gicv3: Insist that redist region capacity matches CPU count, Peter Maydell, 2022/04/08
- [PATCH 07/41] hw/intc/arm_gicv3_its: Implement GITS_BASER2 for GICv4, Peter Maydell, 2022/04/08
- [PATCH 06/41] hw/intc/arm_gicv3_its: Factor out "is intid a valid LPI ID?", Peter Maydell, 2022/04/08
- [PATCH 04/41] hw/intc/arm_gicv3: Report correct PIDR0 values for ID registers, Peter Maydell, 2022/04/08