qemu-arm
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH 05/41] target/arm/cpu.c: ignore VIRQ and VFIQ if no EL2


From: Richard Henderson
Subject: Re: [PATCH 05/41] target/arm/cpu.c: ignore VIRQ and VFIQ if no EL2
Date: Fri, 8 Apr 2022 16:39:35 -0700
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0

On 4/8/22 07:15, Peter Maydell wrote:
In a GICv3, it is impossible for the GIC to deliver a VIRQ or VFIQ to
the CPU unless the CPU has EL2, because VIRQ and VFIQ are only
configurable via EL2-only system registers.  Moreover, in our
implementation we were only calculating and updating the state of the
VIRQ and VFIQ lines in gicv3_cpuif_virt_irq_fiq_update() when those
EL2 system registers changed.  We were therefore able to assert in
arm_cpu_set_irq() that we didn't see a VIRQ or VFIQ line update if
EL2 wasn't present.

This assumption no longer holds with GICv4:
  * even if the CPU does not have EL2 the guest is able to cause the
    GIC to deliver a virtual LPI by programming the ITS (which is a
    silly thing for it to do, but possible)
  * because we now need to recalculate the state of the VIRQ and VFIQ
    lines in more cases than just "some EL2 GIC sysreg was written",
    we will see calls to arm_cpu_set_irq() for "VIRQ is 0, VFIQ is 0"
    even if the guest is not using the virtual LPI parts of the ITS

Remove the assertions, and instead simply ignore the state of the
VIRQ and VFIQ lines if the CPU does not have EL2.

Signed-off-by: Peter Maydell<peter.maydell@linaro.org>
---
  target/arm/cpu.c | 12 ++++++++++--
  1 file changed, 10 insertions(+), 2 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~



reply via email to

[Prev in Thread] Current Thread [Next in Thread]