Re: [PATCH 11/16] target/arm: Add minimal RAS registers

[Richard Henderson]

On 4/11/22 08:49, Peter Maydell wrote:
> > +    { .name = "ERRSELR_EL1", .state = ARM_CP_STATE_BOTH,
> > +      .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 3, .opc2 = 1,
> > +      .access = PL1_RW, .accessfn = access_terr,
> > +      .fieldoffset = offsetof(CPUARMState, cp15.errselr_el1) },
>
> By my reading of the spec we could make ERRSELR_EL1 RAZ/WI, because
> writing an over-large number has a number of behaviours including
> that the value the guest can read back is UNKNOWN. That would save
> having the CPU state struct field.

Good point, I should have read the fine print myself:

If ERRIDR_EL1 indicates that zero error records are implemented, then it is IMPLEMENTATION 
DEFINED whether ERRSELR_EL1 is UNDEFINED or RES 0.

so perhaps it's better to leave it UNDEFINED.


r~