Re: [PATCH v2] target/arm: Disable cryptographic instructions when neon is disabled

[Peter Maydell]

On Wed, 27 Apr 2022 at 10:01, Damien Hedde <damien.hedde@greensocs.com> wrote:
>
> As of now, cryptographic instructions ISAR fields are never cleared so
> we can end up with a cpu with cryptographic instructions but no
> floating-point/neon instructions which is not a possible configuration
> according to ARM specifications.
>
> In QEMU, we have 3 kinds of cpus regarding cryptographic instructions:
> + no support
> + cortex-a57/a72: cryptographic extension is optional,
>   floating-point/neon is not.
> + cortex-a53: crytographic extension is optional as well as
>   floationg-point/neon. But cryptographic requires
>   floating-point/neon support.
>
> Therefore we can safely clear the ISAR fields when neon is disabled.
>
> Note that other arm cpus seem to follow this. For example cortex-a55 is
> like cortex-a53 and cortex-a76/cortex-a710 are like cortex-a57/a72.
>
> Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
> ---



Applied to target-arm.next, thanks.

-- PMM