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[Qemu-commits] [qemu/qemu] 6e288b: rcu: remove qatomic_mb_set, expand co
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From: |
Richard Henderson |
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Subject: |
[Qemu-commits] [qemu/qemu] 6e288b: rcu: remove qatomic_mb_set, expand comments |
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Date: |
Tue, 09 May 2023 09:22:19 -0700 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 6e288b00ef536f87910f76cb1940a8caced69c54
https://github.com/qemu/qemu/commit/6e288b00ef536f87910f76cb1940a8caced69c54
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2023-05-08 (Mon, 08 May 2023)
Changed paths:
M include/qemu/rcu.h
M util/rcu.c
Log Message:
-----------
rcu: remove qatomic_mb_set, expand comments
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 4f7335e21d5170986e20001b9ddb906fe24413f1
https://github.com/qemu/qemu/commit/4f7335e21d5170986e20001b9ddb906fe24413f1
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2023-05-08 (Mon, 08 May 2023)
Changed paths:
M tests/unit/test-aio-multithread.c
Log Message:
-----------
test-aio-multithread: do not use mb_read/mb_set for simple flags
The remaining use of mb_read/mb_set is just to force a thread to exit
eventually. It does not order two memory accesses and therefore can be
just read/set.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 355635c0187d3cc2a0cbb3381e06d61c0bf683ba
https://github.com/qemu/qemu/commit/355635c0187d3cc2a0cbb3381e06d61c0bf683ba
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2023-05-08 (Mon, 08 May 2023)
Changed paths:
M tests/unit/test-aio-multithread.c
Log Message:
-----------
test-aio-multithread: simplify test_multi_co_schedule
Instead of using qatomic_mb_{read,set} mindlessly, just use a per-coroutine
flag that requires no synchronization.
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 8f593ba9c5c96b1790cc6aceb95b5b83bbac92cd
https://github.com/qemu/qemu/commit/8f593ba9c5c96b1790cc6aceb95b5b83bbac92cd
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2023-05-08 (Mon, 08 May 2023)
Changed paths:
M util/rcu.c
Log Message:
-----------
call_rcu: stop using mb_set/mb_read
Use a store-release when enqueuing a new call_rcu, and a load-acquire
when dequeuing; and read the tail after checking that node->next is
consistent, which is the standard message passing pattern and it is
clearer than mb_read/mb_set.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 20f46806b3858b92e9d1b5cf586558d62bd5a913
https://github.com/qemu/qemu/commit/20f46806b3858b92e9d1b5cf586558d62bd5a913
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2023-05-08 (Mon, 08 May 2023)
Changed paths:
M accel/tcg/tb-maint.c
Log Message:
-----------
tb-maint: do not use mb_read/mb_set
The load side can use a relaxed load, which will surely happen before
the work item is run by async_safe_run_on_cpu() or before double-checking
under mmap_lock. The store side can use an atomic RMW operation.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 2f38ff79abac8a0b779e73a025af0d0ec8911a7e
https://github.com/qemu/qemu/commit/2f38ff79abac8a0b779e73a025af0d0ec8911a7e
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2023-05-08 (Mon, 08 May 2023)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: add stanza for Kconfig files
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 8cbfc530bc10a72874ab241faaba8c56e5515532
https://github.com/qemu/qemu/commit/8cbfc530bc10a72874ab241faaba8c56e5515532
Author: Thomas Huth <thuth@redhat.com>
Date: 2023-05-08 (Mon, 08 May 2023)
Changed paths:
M include/qemu/osdep.h
Log Message:
-----------
include/qemu/osdep.h: Bump _WIN32_WINNT to the Windows 8 API
Commit cf60ccc330 ("cutils: Introduce bundle mechanism") abandoned
compatibility with Windows older than 8 - we should reflect this
in our _WIN32_WINNT and set it to the value that corresponds to
Windows 8.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20230504081351.125140-1-thuth@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: cca0a000d06f897411a8af4402e5d0522bbe450b
https://github.com/qemu/qemu/commit/cca0a000d06f897411a8af4402e5d0522bbe450b
Author: Michael Roth <michael.roth@amd.com>
Date: 2023-05-08 (Mon, 08 May 2023)
Changed paths:
M target/i386/cpu.c
Log Message:
-----------
target/i386: allow versioned CPUs to specify new cache_info
New EPYC CPUs versions require small changes to their cache_info's.
Because current QEMU x86 CPU definition does not support versioned
cach_info, we would have to declare a new CPU type for each such case.
To avoid the dup work, add "cache_info" in X86CPUVersionDefinition",
to allow new cache_info pointers to be specified for a new CPU version.
Co-developed-by: Wei Huang <wei.huang2@amd.com>
Signed-off-by: Wei Huang <wei.huang2@amd.com>
Signed-off-by: Michael Roth <michael.roth@amd.com>
Signed-off-by: Babu Moger <babu.moger@amd.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20230504205313.225073-2-babu.moger@amd.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: d7c72735f618a7ee27ee109d8b1468193734606a
https://github.com/qemu/qemu/commit/d7c72735f618a7ee27ee109d8b1468193734606a
Author: Michael Roth <michael.roth@amd.com>
Date: 2023-05-08 (Mon, 08 May 2023)
Changed paths:
M target/i386/cpu.c
Log Message:
-----------
target/i386: Add new EPYC CPU versions with updated cache_info
Introduce new EPYC cpu versions: EPYC-v4 and EPYC-Rome-v3.
The only difference vs. older models is an updated cache_info with
the 'complex_indexing' bit unset, since this bit is not currently
defined for AMD and may cause problems should it be used for
something else in the future. Setting this bit will also cause
CPUID validation failures when running SEV-SNP guests.
Signed-off-by: Michael Roth <michael.roth@amd.com>
Signed-off-by: Babu Moger <babu.moger@amd.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20230504205313.225073-3-babu.moger@amd.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: bb039a230e6a7920d71d21fa9afee2653a678c48
https://github.com/qemu/qemu/commit/bb039a230e6a7920d71d21fa9afee2653a678c48
Author: Babu Moger <babu.moger@amd.com>
Date: 2023-05-08 (Mon, 08 May 2023)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
Log Message:
-----------
target/i386: Add a couple of feature bits in 8000_0008_EBX
Add the following feature bits.
amd-psfd : Predictive Store Forwarding Disable:
PSF is a hardware-based micro-architectural optimization
designed to improve the performance of code execution by
predicting address dependencies between loads and stores.
While SSBD (Speculative Store Bypass Disable) disables both
PSF and speculative store bypass, PSFD only disables PSF.
PSFD may be desirable for the software which is concerned
with the speculative behavior of PSF but desires a smaller
performance impact than setting SSBD.
Depends on the following kernel commit:
b73a54321ad8 ("KVM: x86: Expose Predictive Store Forwarding Disable")
stibp-always-on :
Single Thread Indirect Branch Prediction mode has enhanced
performance and may be left always on.
The documentation for the features are available in the links below.
a. Processor Programming Reference (PPR) for AMD Family 19h Model 01h,
Revision B1 Processors
b. SECURITY ANALYSIS OF AMD PREDICTIVE STORE FORWARDING
Signed-off-by: Babu Moger <babu.moger@amd.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Link:
https://www.amd.com/system/files/documents/security-analysis-predictive-store-forwarding.pdf
Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip
Message-Id: <20230504205313.225073-4-babu.moger@amd.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: b70eec312b185197d639bff689007727e596afd1
https://github.com/qemu/qemu/commit/b70eec312b185197d639bff689007727e596afd1
Author: Babu Moger <babu.moger@amd.com>
Date: 2023-05-08 (Mon, 08 May 2023)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
Log Message:
-----------
target/i386: Add feature bits for CPUID_Fn80000021_EAX
Add the following feature bits.
no-nested-data-bp : Processor ignores nested data breakpoints.
lfence-always-serializing : LFENCE instruction is always serializing.
null-sel-cls-base : Null Selector Clears Base. When this bit is
set, a null segment load clears the segment base.
The documentation for the features are available in the links below.
a. Processor Programming Reference (PPR) for AMD Family 19h Model 01h,
Revision B1 Processors
b. AMD64 Architecture Programmer’s Manual Volumes 1–5 Publication No. Revision
40332 4.05 Date October 2022
Signed-off-by: Babu Moger <babu.moger@amd.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip
Link: https://www.amd.com/system/files/TechDocs/40332_4.05.pdf
Message-Id: <20230504205313.225073-5-babu.moger@amd.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 27f03be6f59d04bd5673ba1e1628b2b490f9a9ff
https://github.com/qemu/qemu/commit/27f03be6f59d04bd5673ba1e1628b2b490f9a9ff
Author: Babu Moger <babu.moger@amd.com>
Date: 2023-05-08 (Mon, 08 May 2023)
Changed paths:
M target/i386/cpu.c
Log Message:
-----------
target/i386: Add missing feature bits in EPYC-Milan model
Add the following feature bits for EPYC-Milan model and bump the version.
vaes : Vector VAES(ENC|DEC), VAES(ENC|DEC)LAST instruction support
vpclmulqdq : Vector VPCLMULQDQ instruction support
stibp-always-on : Single Thread Indirect Branch Prediction Mode has enhanced
performance and may be left Always on
amd-psfd : Predictive Store Forward Disable
no-nested-data-bp : Processor ignores nested data breakpoints
lfence-always-serializing : LFENCE instruction is always serializing
null-sel-clr-base : Null Selector Clears Base. When this bit is
set, a null segment load clears the segment base
These new features will be added in EPYC-Milan-v2. The "-cpu help" output
after the change will be.
x86 EPYC-Milan (alias configured by machine type)
x86 EPYC-Milan-v1 AMD EPYC-Milan Processor
x86 EPYC-Milan-v2 AMD EPYC-Milan Processor
The documentation for the features are available in the links below.
a. Processor Programming Reference (PPR) for AMD Family 19h Model 01h,
Revision B1 Processors
b. SECURITY ANALYSIS OF AMD PREDICTIVE STORE FORWARDING
c. AMD64 Architecture Programmer’s Manual Volumes 1–5 Publication No. Revision
40332 4.05 Date October 2022
Signed-off-by: Babu Moger <babu.moger@amd.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip
Link:
https://www.amd.com/system/files/documents/security-analysis-predictive-store-forwarding.pdf
Link: https://www.amd.com/system/files/TechDocs/40332_4.05.pdf
Message-Id: <20230504205313.225073-6-babu.moger@amd.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 62a798d4bc2c3e767d94670776c77a7df274d7c5
https://github.com/qemu/qemu/commit/62a798d4bc2c3e767d94670776c77a7df274d7c5
Author: Babu Moger <babu.moger@amd.com>
Date: 2023-05-08 (Mon, 08 May 2023)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
Log Message:
-----------
target/i386: Add VNMI and automatic IBRS feature bits
Add the following featute bits.
vnmi: Virtual NMI (VNMI) allows the hypervisor to inject the NMI into the
guest without using Event Injection mechanism meaning not required to
track the guest NMI and intercepting the IRET.
The presence of this feature is indicated via the CPUID function
0x8000000A_EDX[25].
automatic-ibrs :
The AMD Zen4 core supports a new feature called Automatic IBRS.
It is a "set-and-forget" feature that means that, unlike e.g.,
s/w-toggled SPEC_CTRL.IBRS, h/w manages its IBRS mitigation
resources automatically across CPL transitions.
The presence of this feature is indicated via the CPUID function
0x80000021_EAX[8].
The documention for the features are available in the links below.
a. Processor Programming Reference (PPR) for AMD Family 19h Model 01h,
Revision B1 Processors
b. AMD64 Architecture Programmer’s Manual Volumes 1–5 Publication No. Revision
40332 4.05 Date October 2022
Signed-off-by: Santosh Shukla <santosh.shukla@amd.com>
Signed-off-by: Kim Phillips <kim.phillips@amd.com>
Signed-off-by: Babu Moger <babu.moger@amd.com>
Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip
Link: https://www.amd.com/system/files/TechDocs/40332_4.05.pdf
Message-Id: <20230504205313.225073-7-babu.moger@amd.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 166b1741884dd4fd7090b753cd7333868457a29b
https://github.com/qemu/qemu/commit/166b1741884dd4fd7090b753cd7333868457a29b
Author: Babu Moger <babu.moger@amd.com>
Date: 2023-05-08 (Mon, 08 May 2023)
Changed paths:
M target/i386/cpu.c
Log Message:
-----------
target/i386: Add EPYC-Genoa model to support Zen 4 processor series
Adds the support for AMD EPYC Genoa generation processors. The model
display for the new processor will be EPYC-Genoa.
Adds the following new feature bits on top of the feature bits from
the previous generation EPYC models.
avx512f : AVX-512 Foundation instruction
avx512dq : AVX-512 Doubleword & Quadword Instruction
avx512ifma : AVX-512 Integer Fused Multiply Add instruction
avx512cd : AVX-512 Conflict Detection instruction
avx512bw : AVX-512 Byte and Word Instructions
avx512vl : AVX-512 Vector Length Extension Instructions
avx512vbmi : AVX-512 Vector Byte Manipulation Instruction
avx512_vbmi2 : AVX-512 Additional Vector Byte Manipulation Instruction
gfni : AVX-512 Galois Field New Instructions
avx512_vnni : AVX-512 Vector Neural Network Instructions
avx512_bitalg : AVX-512 Bit Algorithms, add bit algorithms Instructions
avx512_vpopcntdq: AVX-512 AVX-512 Vector Population Count Doubleword and
Quadword Instructions
avx512_bf16 : AVX-512 BFLOAT16 instructions
la57 : 57-bit virtual address support (5-level Page Tables)
vnmi : Virtual NMI (VNMI) allows the hypervisor to inject the NMI
into the guest without using Event Injection mechanism
meaning not required to track the guest NMI and intercepting
the IRET.
auto-ibrs : The AMD Zen4 core supports a new feature called Automatic
IBRS.
It is a "set-and-forget" feature that means that, unlike e.g.,
s/w-toggled SPEC_CTRL.IBRS, h/w manages its IBRS mitigation
resources automatically across CPL transitions.
Signed-off-by: Babu Moger <babu.moger@amd.com>
Message-Id: <20230504205313.225073-8-babu.moger@amd.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 23b2a3be999bd53cfac63325b8bc02a205f1fe5b
https://github.com/qemu/qemu/commit/23b2a3be999bd53cfac63325b8bc02a205f1fe5b
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2023-05-08 (Mon, 08 May 2023)
Changed paths:
M docs/devel/kconfig.rst
Log Message:
-----------
docs: clarify --without-default-devices
--without-default-devices is a specialized option that should only be used
when configs/devices/ is changed manually.
Explain the model towards which we should tend, with respect to failures
to start guests and to run "make check".
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: ef709860ea12ec59c4cd7373bd2fd7a4e50143ee
https://github.com/qemu/qemu/commit/ef709860ea12ec59c4cd7373bd2fd7a4e50143ee
Author: Paolo Bonzini <pbonzini@redhat.com>
Date: 2023-05-08 (Mon, 08 May 2023)
Changed paths:
M meson.build
Log Message:
-----------
meson: leave unnecessary modules out of the build
meson.build files choose whether to build modules based on foo.found()
expressions. If a feature is enabled (e.g. --enable-gtk), these expressions
are true even if the code is not used by any emulator, and this results
in an unexpected difference between modular and non-modular builds.
For non-modular builds, the files are not included in any binary, and
therefore the source files are never processed. For modular builds,
however, all .so files are unconditionally built by default, and therefore
a normal "make" tries to build them. However, the corresponding trace-*.h
files are absent due to this conditional:
if have_system
trace_events_subdirs += [
...
'ui',
...
]
endif
which was added to avoid wasting time running tracetool on unused trace-events
files. This causes a compilation failure; fix it by skipping module builds
entirely if (depending on the module directory) have_block or have_system
are false.
Reported-by: Michael Tokarev <mjt@tls.msk.ru>
Cc: qemu-stable@nongnu.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Commit: 577e648bdb524d1984659baf1bd6165de2edae83
https://github.com/qemu/qemu/commit/577e648bdb524d1984659baf1bd6165de2edae83
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2023-05-09 (Tue, 09 May 2023)
Changed paths:
M MAINTAINERS
M accel/tcg/tb-maint.c
M docs/devel/kconfig.rst
M include/qemu/osdep.h
M include/qemu/rcu.h
M meson.build
M target/i386/cpu.c
M target/i386/cpu.h
M tests/unit/test-aio-multithread.c
M util/rcu.c
Log Message:
-----------
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* target/i386: improved EPYC models
* more removal of mb_read/mb_set
* bump _WIN32_WINNT to the Windows 8 API
* fix for modular builds with --disable-system
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# gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
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# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [undefined]
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* tag 'for-upstream' of https://gitlab.com/bonzini/qemu:
meson: leave unnecessary modules out of the build
docs: clarify --without-default-devices
target/i386: Add EPYC-Genoa model to support Zen 4 processor series
target/i386: Add VNMI and automatic IBRS feature bits
target/i386: Add missing feature bits in EPYC-Milan model
target/i386: Add feature bits for CPUID_Fn80000021_EAX
target/i386: Add a couple of feature bits in 8000_0008_EBX
target/i386: Add new EPYC CPU versions with updated cache_info
target/i386: allow versioned CPUs to specify new cache_info
include/qemu/osdep.h: Bump _WIN32_WINNT to the Windows 8 API
MAINTAINERS: add stanza for Kconfig files
tb-maint: do not use mb_read/mb_set
call_rcu: stop using mb_set/mb_read
test-aio-multithread: simplify test_multi_co_schedule
test-aio-multithread: do not use mb_read/mb_set for simple flags
rcu: remove qatomic_mb_set, expand comments
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/ef73c6e8601a...577e648bdb52