[Qemu-commits] [qemu/qemu] a0f06a: target/m68k: Fix gen_load_fp for OS

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[Qemu-commits] [qemu/qemu] a0f06a: target/m68k: Fix gen_load_fp for OS_L

From:	Richard Henderson
Subject:	[Qemu-commits] [qemu/qemu] a0f06a: target/m68k: Fix gen_load_fp for OS_LONG
Date:	Thu, 11 May 2023 05:28:12 -0700
  Branch: refs/heads/master
  Home:   https://github.com/qemu/qemu
  Commit: a0f06a6226c463137acc5c187aef2c268f389282
      
https://github.com/qemu/qemu/commit/a0f06a6226c463137acc5c187aef2c268f389282
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M target/m68k/translate.c

  Log Message:
  -----------
  target/m68k: Fix gen_load_fp for OS_LONG

Case was accidentally dropped in b7a94da9550b.

Tested-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 8c313254e61ed47a1bf4a2db714b25cdd94fbcce
      
https://github.com/qemu/qemu/commit/8c313254e61ed47a1bf4a2db714b25cdd94fbcce
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M accel/tcg/cputlb.c

  Log Message:
  -----------
  accel/tcg: Fix atomic_mmu_lookup for reads

A copy-paste bug had us looking at the victim cache for writes.

Cc: qemu-stable@nongnu.org
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Fixes: 08dff435e2 ("tcg: Probe the proper permissions for atomic ops")
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20230505204049.352469-1-richard.henderson@linaro.org>


  Commit: 692aba8d769585a6cd9e37c101af73dbd1482f7f
      
https://github.com/qemu/qemu/commit/692aba8d769585a6cd9e37c101af73dbd1482f7f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M disas.c

  Log Message:
  -----------
  disas: Fix tabs and braces in disas.c

Fix these before moving the file, for checkpatch.pl.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230510170812.663149-1-richard.henderson@linaro.org>


  Commit: f779026478773da05e3f5b4621dddc5c6d6542dc
      
https://github.com/qemu/qemu/commit/f779026478773da05e3f5b4621dddc5c6d6542dc
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    R disas.c
    A disas/disas.c
    M disas/meson.build
    M meson.build

  Log Message:
  -----------
  disas: Move disas.c to disas/

Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230503072331.1747057-80-richard.henderson@linaro.org>


  Commit: b6235a759a4552d21c5b68d16c894aa5b96d4b96
      
https://github.com/qemu/qemu/commit/b6235a759a4552d21c5b68d16c894aa5b96d4b96
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M bsd-user/elfload.c
    M disas/disas.c
    M include/disas/disas.h
    M linux-user/elfload.c

  Log Message:
  -----------
  disas: Remove target_ulong from the interface

Use uint64_t for the pc, and size_t for the size.

Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230503072331.1747057-81-richard.henderson@linaro.org>


  Commit: 45dfbd4320cc29a06b4921fe21a145e9a4f87323
      
https://github.com/qemu/qemu/commit/45dfbd4320cc29a06b4921fe21a145e9a4f87323
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M disas/disas.c
    M include/disas/disas.h

  Log Message:
  -----------
  disas: Remove target-specific headers

Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230503072331.1747057-83-richard.henderson@linaro.org>


  Commit: e22d3c48db6fea230a24881a6a29766f2156283a
      
https://github.com/qemu/qemu/commit/e22d3c48db6fea230a24881a6a29766f2156283a
  Author: Thomas Huth <thuth@redhat.com>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    A disas/disas-internal.h
    A disas/disas-mon.c
    M disas/disas.c
    M disas/meson.build

  Log Message:
  -----------
  disas: Move softmmu specific code to separate file

We'd like to move disas.c into the common code source set, where
CONFIG_USER_ONLY is not available anymore. So we have to move
the related code into a separate file instead.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20230508133745.109463-2-thuth@redhat.com>
[rth: Type change done in a separate patch]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: eb0153efa6fa58b2c9d891b17766dbedc10e31b5
      
https://github.com/qemu/qemu/commit/eb0153efa6fa58b2c9d891b17766dbedc10e31b5
  Author: Thomas Huth <thuth@redhat.com>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M disas/disas.c
    M disas/meson.build

  Log Message:
  -----------
  disas: Move disas.c into the target-independent source set

Use target_words_bigendian() instead of an ifdef.

Remove CONFIG_RISCV_DIS from the check for riscv as a host; this is
a poisoned identifier, and anyway will always be set by meson.build
when building on a riscv host.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20230508133745.109463-3-thuth@redhat.com>
[rth: Type change done in a separate patch]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 370ed600296982a0248b091915c8e8893508d8a3
      
https://github.com/qemu/qemu/commit/370ed600296982a0248b091915c8e8893508d8a3
  Author: Jamie Iles <quic_jiles@quicinc.com>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M cpus-common.c
    M include/exec/cpu-common.h
    M linux-user/elfload.c
    M migration/dirtyrate.c
    M trace/control-target.c

  Log Message:
  -----------
  cpu: expose qemu_cpu_list_lock for lock-guard use

Expose qemu_cpu_list_lock globally so that we can use
WITH_QEMU_LOCK_GUARD and QEMU_LOCK_GUARD to simplify a few code paths
now and in future.

Signed-off-by: Jamie Iles <quic_jiles@quicinc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427020925.51003-2-quic_jiles@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 83ecdb18eb65ed57239b87f3898ae92a590d0077
      
https://github.com/qemu/qemu/commit/83ecdb18eb65ed57239b87f3898ae92a590d0077
  Author: Jamie Iles <quic_jiles@quicinc.com>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M accel/tcg/tcg-accel-ops-icount.c
    M accel/tcg/tcg-accel-ops-icount.h
    M accel/tcg/tcg-accel-ops-rr.c
    M replay/replay.c

  Log Message:
  -----------
  accel/tcg/tcg-accel-ops-rr: ensure fairness with icount

The round-robin scheduler will iterate over the CPU list with an
assigned budget until the next timer expiry and may exit early because
of a TB exit.  This is fine under normal operation but with icount
enabled and SMP it is possible for a CPU to be starved of run time and
the system live-locks.

For example, booting a riscv64 platform with '-icount
shift=0,align=off,sleep=on -smp 2' we observe a livelock once the kernel
has timers enabled and starts performing TLB shootdowns.  In this case
we have CPU 0 in M-mode with interrupts disabled sending an IPI to CPU
1.  As we enter the TCG loop, we assign the icount budget to next timer
interrupt to CPU 0 and begin executing where the guest is sat in a busy
loop exhausting all of the budget before we try to execute CPU 1 which
is the target of the IPI but CPU 1 is left with no budget with which to
execute and the process repeats.

We try here to add some fairness by splitting the budget across all of
the CPUs on the thread fairly before entering each one.  The CPU count
is cached on CPU list generation ID to avoid iterating the list on each
loop iteration.  With this change it is possible to boot an SMP rv64
guest with icount enabled and no hangs.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Jamie Iles <quic_jiles@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427020925.51003-3-quic_jiles@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 530074c6c1134a8ca488f50af82788a634a1e552
      
https://github.com/qemu/qemu/commit/530074c6c1134a8ca488f50af82788a634a1e552
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: Introduce prepare_host_addr

Merge tcg_out_tlb_load, add_qemu_ldst_label,
tcg_out_test_alignment, and some code that lived in both
tcg_out_qemu_ld and tcg_out_qemu_st into one function
that returns HostAddress and TCGLabelQemuLdst structures.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 1fac4648fed615f0507368633bb7d0a9821873d6
      
https://github.com/qemu/qemu/commit/1fac4648fed615f0507368633bb7d0a9821873d6
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: Use indexed addressing for softmmu fast path

Since tcg_out_{ld,st}_helper_args, the slow path no longer requires
the address argument to be set up by the tlb load sequence.  Use a
plain load for the addend and indexed addressing with the original
input address register.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 1e612dd66a3915d9560a13341b3e32a2bafbff83
      
https://github.com/qemu/qemu/commit/1e612dd66a3915d9560a13341b3e32a2bafbff83
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/aarch64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/aarch64: Introduce prepare_host_addr

Merge tcg_out_tlb_load, add_qemu_ldst_label, tcg_out_test_alignment,
and some code that lived in both tcg_out_qemu_ld and tcg_out_qemu_st
into one function that returns HostAddress and TCGLabelQemuLdst structures.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 7131d3cf72af0ecd54d325cbe2d88db144e52fed
      
https://github.com/qemu/qemu/commit/7131d3cf72af0ecd54d325cbe2d88db144e52fed
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/arm/tcg-target.c.inc

  Log Message:
  -----------
  tcg/arm: Introduce prepare_host_addr

Merge tcg_out_tlb_load, add_qemu_ldst_label, and some code that lived
in both tcg_out_qemu_ld and tcg_out_qemu_st into one function that
returns HostAddress and TCGLabelQemuLdst structures.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: e63eed328f20e114c009f0dda98fdc6a58312e1c
      
https://github.com/qemu/qemu/commit/e63eed328f20e114c009f0dda98fdc6a58312e1c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/loongarch64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/loongarch64: Introduce prepare_host_addr

Merge tcg_out_tlb_load, add_qemu_ldst_label, tcg_out_test_alignment,
tcg_out_zext_addr_if_32_bit, and some code that lived in both
tcg_out_qemu_ld and tcg_out_qemu_st into one function that returns
HostAddress and TCGLabelQemuLdst structures.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 5b7208daa0b35eae3b8adf5cabc695bb895caeba
      
https://github.com/qemu/qemu/commit/5b7208daa0b35eae3b8adf5cabc695bb895caeba
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/mips/tcg-target.c.inc

  Log Message:
  -----------
  tcg/mips: Introduce prepare_host_addr

Merge tcg_out_tlb_load, add_qemu_ldst_label, tcg_out_test_alignment,
and some code that lived in both tcg_out_qemu_ld and tcg_out_qemu_st
into one function that returns HostAddress and TCGLabelQemuLdst structures.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 7069e036999b78f83f0303e275c1c4413dfa10a3
      
https://github.com/qemu/qemu/commit/7069e036999b78f83f0303e275c1c4413dfa10a3
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/ppc/tcg-target.c.inc

  Log Message:
  -----------
  tcg/ppc: Introduce prepare_host_addr

Merge tcg_out_tlb_load, add_qemu_ldst_label, tcg_out_test_alignment,
and some code that lived in both tcg_out_qemu_ld and tcg_out_qemu_st
into one function that returns HostAddress and TCGLabelQemuLdst structures.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 001dddfe0ed9bbc099deab1fde829fc9292f4d25
      
https://github.com/qemu/qemu/commit/001dddfe0ed9bbc099deab1fde829fc9292f4d25
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/riscv/tcg-target.c.inc

  Log Message:
  -----------
  tcg/riscv: Introduce prepare_host_addr

Merge tcg_out_tlb_load, add_qemu_ldst_label, tcg_out_test_alignment,
and some code that lived in both tcg_out_qemu_ld and tcg_out_qemu_st
into one function that returns TCGReg and TCGLabelQemuLdst.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 0741b25e4ee703c66b648eea5650ca833eae03db
      
https://github.com/qemu/qemu/commit/0741b25e4ee703c66b648eea5650ca833eae03db
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/s390x/tcg-target.c.inc

  Log Message:
  -----------
  tcg/s390x: Introduce prepare_host_addr

Merge tcg_out_tlb_load, add_qemu_ldst_label, tcg_out_test_alignment,
tcg_prepare_user_ldst, and some code that lived in both tcg_out_qemu_ld
and tcg_out_qemu_st into one function that returns HostAddress and
TCGLabelQemuLdst structures.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 8429a1ca8f315394b2a68b96812b1dc9c60070fd
      
https://github.com/qemu/qemu/commit/8429a1ca8f315394b2a68b96812b1dc9c60070fd
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Add routines for calling slow-path helpers

Add tcg_out_ld_helper_args, tcg_out_ld_helper_ret,
and tcg_out_st_helper_args.  These and their subroutines
use the existing knowledge of the host function call abi
to load the function call arguments and return results.

These will be used to simplify the backends in turn.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: da8ab70ad17762e1ad1c4de01f981adebd26f851
      
https://github.com/qemu/qemu/commit/da8ab70ad17762e1ad1c4de01f981adebd26f851
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: Convert tcg_out_qemu_ld_slow_path

Use tcg_out_ld_helper_args and tcg_out_ld_helper_ret.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 0036e54e7abfd8ea7f3aeb7db2daa23b25cc8094
      
https://github.com/qemu/qemu/commit/0036e54e7abfd8ea7f3aeb7db2daa23b25cc8094
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/i386/tcg-target.c.inc

  Log Message:
  -----------
  tcg/i386: Convert tcg_out_qemu_st_slow_path

Use tcg_out_st_helper_args.  This eliminates the use of a tail call to
the store helper.  This may or may not be an improvement, depending on
the call/return branch prediction of the host microarchitecture.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 6e96422b14a462da0089768baa91529f4192212c
      
https://github.com/qemu/qemu/commit/6e96422b14a462da0089768baa91529f4192212c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/aarch64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/aarch64: Convert tcg_out_qemu_{ld,st}_slow_path

Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret,
and tcg_out_st_helper_args.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 74c17067329042eb48b0e972b8a9292c85f2d244
      
https://github.com/qemu/qemu/commit/74c17067329042eb48b0e972b8a9292c85f2d244
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/arm/tcg-target.c.inc

  Log Message:
  -----------
  tcg/arm: Convert tcg_out_qemu_{ld,st}_slow_path

Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret,
and tcg_out_st_helper_args.  This allows our local
tcg_out_arg_* infrastructure to be removed.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 338b9e09503714016f9c5c4b649b007e721ca057
      
https://github.com/qemu/qemu/commit/338b9e09503714016f9c5c4b649b007e721ca057
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/loongarch64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/loongarch64: Convert tcg_out_qemu_{ld,st}_slow_path

Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret,
and tcg_out_st_helper_args.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: f07aaf4856ee642f9f566bc26d8547819871516f
      
https://github.com/qemu/qemu/commit/f07aaf4856ee642f9f566bc26d8547819871516f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/mips/tcg-target.c.inc

  Log Message:
  -----------
  tcg/mips: Convert tcg_out_qemu_{ld,st}_slow_path

Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret,
and tcg_out_st_helper_args.  This allows our local
tcg_out_arg_* infrastructure to be removed.

We are no longer filling the call or return branch
delay slots, nor are we tail-calling for the store,
but this seems a small price to pay.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: ec3894191274df2b61219053010d93072ca5b9f2
      
https://github.com/qemu/qemu/commit/ec3894191274df2b61219053010d93072ca5b9f2
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/ppc/tcg-target.c.inc

  Log Message:
  -----------
  tcg/ppc: Convert tcg_out_qemu_{ld,st}_slow_path

Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret,
and tcg_out_st_helper_args.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 61b6daafb49148690fdc82e570b3daabfbaaf8a9
      
https://github.com/qemu/qemu/commit/61b6daafb49148690fdc82e570b3daabfbaaf8a9
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/riscv/tcg-target.c.inc

  Log Message:
  -----------
  tcg/riscv: Convert tcg_out_qemu_{ld,st}_slow_path

Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret,
and tcg_out_st_helper_args.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: eb491329f6eea979e95db191b5a4b44a09b008bf
      
https://github.com/qemu/qemu/commit/eb491329f6eea979e95db191b5a4b44a09b008bf
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/s390x/tcg-target.c.inc

  Log Message:
  -----------
  tcg/s390x: Convert tcg_out_qemu_{ld,st}_slow_path

Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret,
and tcg_out_st_helper_args.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: e3205306d89cd4abcd4d88cbdad38046554249db
      
https://github.com/qemu/qemu/commit/e3205306d89cd4abcd4d88cbdad38046554249db
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/loongarch64/tcg-target-con-set.h
    M tcg/loongarch64/tcg-target-con-str.h
    M tcg/loongarch64/tcg-target.c.inc

  Log Message:
  -----------
  tcg/loongarch64: Simplify constraints on qemu_ld/st

The softmmu tlb uses TCG_REG_TMP[0-2], not any of the normally available
registers.  Now that we handle overlap betwen inputs and helper arguments,
we can allow any allocatable reg.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: a79956219f264945d06a540387a8f72f5ba4953b
      
https://github.com/qemu/qemu/commit/a79956219f264945d06a540387a8f72f5ba4953b
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/mips/tcg-target.c.inc
    M tcg/mips/tcg-target.h

  Log Message:
  -----------
  tcg/mips: Remove MO_BSWAP handling

While performing the load in the delay slot of the call to the common
bswap helper function is cute, it is not worth the added complexity.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 2f2a3d1d0b11416aa39cd6127d9632318c7e345b
      
https://github.com/qemu/qemu/commit/2f2a3d1d0b11416aa39cd6127d9632318c7e345b
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/mips/tcg-target.c.inc

  Log Message:
  -----------
  tcg/mips: Reorg tlb load within prepare_host_addr

Compare the address vs the tlb entry with sign-extended values.
This simplifies the page+alignment mask constant, and the
generation of the last byte address for the misaligned test.

Move the tlb addend load up, and the zero-extension down.

This frees up a register, which allows us use TMP3 as the returned base
address register instead of A0, which we were using as a 5th temporary.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: f48cc9020b6a1b41f7ccc639a09fecc5a6b42ad1
      
https://github.com/qemu/qemu/commit/f48cc9020b6a1b41f7ccc639a09fecc5a6b42ad1
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/mips/tcg-target-con-set.h
    M tcg/mips/tcg-target-con-str.h
    M tcg/mips/tcg-target.c.inc

  Log Message:
  -----------
  tcg/mips: Simplify constraints on qemu_ld/st

The softmmu tlb uses TCG_REG_TMP[0-3], not any of the normally available
registers.  Now that we handle overlap betwen inputs and helper arguments,
and have eliminated use of A0, we can allow any allocatable reg.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 01a112e2e9f8c969b3d190e1fd2faf24644a771c
      
https://github.com/qemu/qemu/commit/01a112e2e9f8c969b3d190e1fd2faf24644a771c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/ppc/tcg-target.c.inc

  Log Message:
  -----------
  tcg/ppc: Reorg tcg_out_tlb_read

Allocate TCG_REG_TMP2.  Use R0, TMP1, TMP2 instead of any of
the normally allocated registers for the tlb load.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: b41b43a4773c64c40b563c4da49285487f1ca1d8
      
https://github.com/qemu/qemu/commit/b41b43a4773c64c40b563c4da49285487f1ca1d8
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/ppc/tcg-target-con-set.h
    M tcg/ppc/tcg-target-con-str.h
    M tcg/ppc/tcg-target.c.inc

  Log Message:
  -----------
  tcg/ppc: Adjust constraints on qemu_ld/st

The softmmu tlb uses TCG_REG_{TMP1,TMP2,R0}, not any of the normally
available registers.  Now that we handle overlap betwen inputs and
helper arguments, we can allow any allocatable reg.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 6e21aa2dcdcb647a13ef32180e6574fb702db4c3
      
https://github.com/qemu/qemu/commit/6e21aa2dcdcb647a13ef32180e6574fb702db4c3
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/ppc/tcg-target-con-str.h

  Log Message:
  -----------
  tcg/ppc: Remove unused constraints A, B, C, D

These constraints have not been used for quite some time.

Fixes: 77b73de67632 ("Use rem/div[u]_i32 drop div[u]2_i32")
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 3dedb7201c292d340ac73fb0e52179e3690fb0c8
      
https://github.com/qemu/qemu/commit/3dedb7201c292d340ac73fb0e52179e3690fb0c8
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/ppc/tcg-target-con-str.h
    M tcg/ppc/tcg-target.c.inc

  Log Message:
  -----------
  tcg/ppc: Remove unused constraint J

Never used since its introduction.

Fixes: 3d582c6179c ("tcg-ppc64: Rearrange integer constant constraints")
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: f0f43534f7f5beb92788951da6944faad154c6a2
      
https://github.com/qemu/qemu/commit/f0f43534f7f5beb92788951da6944faad154c6a2
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/riscv/tcg-target-con-set.h
    M tcg/riscv/tcg-target-con-str.h
    M tcg/riscv/tcg-target.c.inc

  Log Message:
  -----------
  tcg/riscv: Simplify constraints on qemu_ld/st

The softmmu tlb uses TCG_REG_TMP[0-2], not any of the normally available
registers.  Now that we handle overlap betwen inputs and helper arguments,
we can allow any allocatable reg.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 8b1b45971ff6a2d98d2737279fbbc4173e0dbe8c
      
https://github.com/qemu/qemu/commit/8b1b45971ff6a2d98d2737279fbbc4173e0dbe8c
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/s390x/tcg-target.c.inc

  Log Message:
  -----------
  tcg/s390x: Use ALGFR in constructing softmmu host address

Rather than zero-extend the guest address into a register,
use an add instruction which zero-extends the second input.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 94901422840c2a33e7889fd87540e65bc9028283
      
https://github.com/qemu/qemu/commit/94901422840c2a33e7889fd87540e65bc9028283
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M tcg/s390x/tcg-target-con-set.h
    M tcg/s390x/tcg-target-con-str.h
    M tcg/s390x/tcg-target.c.inc

  Log Message:
  -----------
  tcg/s390x: Simplify constraints on qemu_ld/st

Adjust the softmmu tlb to use R0+R1, not any of the normally available
registers.  Since we handle overlap betwen inputs and helper arguments,
we can allow any allocatable reg.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 3ec02c1f0f539ea117817484f4a352010edaf9e2
      
https://github.com/qemu/qemu/commit/3ec02c1f0f539ea117817484f4a352010edaf9e2
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M target/mips/tcg/nanomips_translate.c.inc

  Log Message:
  -----------
  target/mips: Add MO_ALIGN to gen_llwp, gen_scwp

These are atomic operations, so mark as requiring alignment.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 0d5bede4680c88a02213c3cc13dd7a74453a71b5
      
https://github.com/qemu/qemu/commit/0d5bede4680c88a02213c3cc13dd7a74453a71b5
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M target/mips/tcg/micromips_translate.c.inc
    M target/mips/tcg/mips16e_translate.c.inc
    M target/mips/tcg/mxu_translate.c
    M target/mips/tcg/nanomips_translate.c.inc

  Log Message:
  -----------
  target/mips: Add missing default_tcg_memop_mask

Memory operations that are not already aligned, or otherwise
marked up, require addition of ctx->default_tcg_memop_mask.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: fc49723769dca4edf1348e1eec96ad4b810260ba
      
https://github.com/qemu/qemu/commit/fc49723769dca4edf1348e1eec96ad4b810260ba
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M target/mips/tcg/nanomips_translate.c.inc

  Log Message:
  -----------
  target/mips: Use MO_ALIGN instead of 0

The opposite of MO_UNALN is MO_ALIGN.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 0e85e81b42e52e6e584aebe98c5b187653a577c1
      
https://github.com/qemu/qemu/commit/0e85e81b42e52e6e584aebe98c5b187653a577c1
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M configs/targets/mips-linux-user.mak
    M configs/targets/mips-softmmu.mak
    M configs/targets/mips64-linux-user.mak
    M configs/targets/mips64-softmmu.mak
    M configs/targets/mips64el-linux-user.mak
    M configs/targets/mips64el-softmmu.mak
    M configs/targets/mipsel-linux-user.mak
    M configs/targets/mipsel-softmmu.mak
    M configs/targets/mipsn32-linux-user.mak
    M configs/targets/mipsn32el-linux-user.mak

  Log Message:
  -----------
  target/mips: Remove TARGET_ALIGNED_ONLY

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: a978c37b275a6f7fb21d5bf6d46dca56b96ec7b0
      
https://github.com/qemu/qemu/commit/a978c37b275a6f7fb21d5bf6d46dca56b96ec7b0
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M configs/targets/nios2-softmmu.mak
    M target/nios2/translate.c

  Log Message:
  -----------
  target/nios2: Remove TARGET_ALIGNED_ONLY

In gen_ldx/gen_stx, the only two locations for memory operations,
mark the operation as either aligned (softmmu) or unaligned
(user-only, as if emulated by the kernel).

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 03a0d87e8ddc2577151b02d5b93c577ac48b133a
      
https://github.com/qemu/qemu/commit/03a0d87e8ddc2577151b02d5b93c577ac48b133a
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M target/sh4/translate.c

  Log Message:
  -----------
  target/sh4: Use MO_ALIGN where required

Mark all memory operations that are not already marked with UNALIGN.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 8244189419f9bf290b03a5993401d722533de972
      
https://github.com/qemu/qemu/commit/8244189419f9bf290b03a5993401d722533de972
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M configs/targets/sh4-linux-user.mak
    M configs/targets/sh4-softmmu.mak
    M configs/targets/sh4eb-linux-user.mak
    M configs/targets/sh4eb-softmmu.mak

  Log Message:
  -----------
  target/sh4: Remove TARGET_ALIGNED_ONLY

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 1fceff9c3ca5960748f7346b3cd75e9d2620eaed
      
https://github.com/qemu/qemu/commit/1fceff9c3ca5960748f7346b3cd75e9d2620eaed
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M include/exec/memop.h
    M include/exec/poison.h
    M tcg/tcg.c

  Log Message:
  -----------
  tcg: Remove TARGET_ALIGNED_ONLY

All uses have now been expunged.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 9877ea05de9cdce6a5da87175d8455832f8148dc
      
https://github.com/qemu/qemu/commit/9877ea05de9cdce6a5da87175d8455832f8148dc
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M accel/tcg/cpu-exec-common.c
    M accel/tcg/internal.h
    M accel/tcg/tb-maint.c

  Log Message:
  -----------
  accel/tcg: Add cpu_in_serial_context

Like cpu_in_exclusive_context, but also true if
there is no other cpu against which we could race.

Use it in tb_flush as a direct replacement.
Use it in cpu_loop_exit_atomic to ensure that there
is no loop against cpu_exec_step_atomic.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 0b3c75ad1a21574cc55b0c095a7dc21e2d27ffc8
      
https://github.com/qemu/qemu/commit/0b3c75ad1a21574cc55b0c095a7dc21e2d27ffc8
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M accel/tcg/cputlb.c
    M include/exec/cpu-defs.h
    M include/exec/cpu_ldst.h

  Log Message:
  -----------
  accel/tcg: Introduce tlb_read_idx

Instead of playing with offsetof in various places, use
MMUAccessType to index an array.  This is easily defined
instead of the previous dummy padding array in the union.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 8cfdacaa1642ed18e48935f7536f8d233db8efcc
      
https://github.com/qemu/qemu/commit/8cfdacaa1642ed18e48935f7536f8d233db8efcc
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M accel/tcg/cputlb.c

  Log Message:
  -----------
  accel/tcg: Reorg system mode load helpers

Instead of trying to unify all operations on uint64_t, pull out
mmu_lookup() to perform the basic tlb hit and resolution.
Create individual functions to handle access by size.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 592134617c98f37b8b39c6dd684e5a1832c071d2
      
https://github.com/qemu/qemu/commit/592134617c98f37b8b39c6dd684e5a1832c071d2
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M accel/tcg/cputlb.c

  Log Message:
  -----------
  accel/tcg: Reorg system mode store helpers

Instead of trying to unify all operations on uint64_t, use
mmu_lookup() to perform the basic tlb hit and resolution.
Create individual functions to handle access by size.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 335dfd253fc242b009a1b9b5d4fffbf4ea52928d
      
https://github.com/qemu/qemu/commit/335dfd253fc242b009a1b9b5d4fffbf4ea52928d
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M target/loongarch/csr_helper.c
    M target/loongarch/iocsr_helper.c

  Log Message:
  -----------
  target/loongarch: Do not include tcg-ldst.h

This header is supposed to be private to tcg and in fact
does not need to be included here at all.

Reviewed-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: 278238505d28d292927bff7683f39fb4fbca7fd1
      
https://github.com/qemu/qemu/commit/278238505d28d292927bff7683f39fb4fbca7fd1
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2023-05-11 (Thu, 11 May 2023)

  Changed paths:
    M accel/tcg/cpu-exec-common.c
    M accel/tcg/cputlb.c
    M accel/tcg/internal.h
    M accel/tcg/tb-maint.c
    M accel/tcg/tcg-accel-ops-icount.c
    M accel/tcg/tcg-accel-ops-icount.h
    M accel/tcg/tcg-accel-ops-rr.c
    M bsd-user/elfload.c
    M configs/targets/mips-linux-user.mak
    M configs/targets/mips-softmmu.mak
    M configs/targets/mips64-linux-user.mak
    M configs/targets/mips64-softmmu.mak
    M configs/targets/mips64el-linux-user.mak
    M configs/targets/mips64el-softmmu.mak
    M configs/targets/mipsel-linux-user.mak
    M configs/targets/mipsel-softmmu.mak
    M configs/targets/mipsn32-linux-user.mak
    M configs/targets/mipsn32el-linux-user.mak
    M configs/targets/nios2-softmmu.mak
    M configs/targets/sh4-linux-user.mak
    M configs/targets/sh4-softmmu.mak
    M configs/targets/sh4eb-linux-user.mak
    M configs/targets/sh4eb-softmmu.mak
    M cpus-common.c
    R disas.c
    A disas/disas-internal.h
    A disas/disas-mon.c
    A disas/disas.c
    M disas/meson.build
    M include/disas/disas.h
    M include/exec/cpu-common.h
    M include/exec/cpu-defs.h
    M include/exec/cpu_ldst.h
    M include/exec/memop.h
    M include/exec/poison.h
    M linux-user/elfload.c
    M meson.build
    M migration/dirtyrate.c
    M replay/replay.c
    M target/loongarch/csr_helper.c
    M target/loongarch/iocsr_helper.c
    M target/m68k/translate.c
    M target/mips/tcg/micromips_translate.c.inc
    M target/mips/tcg/mips16e_translate.c.inc
    M target/mips/tcg/mxu_translate.c
    M target/mips/tcg/nanomips_translate.c.inc
    M target/nios2/translate.c
    M target/sh4/translate.c
    M tcg/aarch64/tcg-target.c.inc
    M tcg/arm/tcg-target.c.inc
    M tcg/i386/tcg-target.c.inc
    M tcg/loongarch64/tcg-target-con-set.h
    M tcg/loongarch64/tcg-target-con-str.h
    M tcg/loongarch64/tcg-target.c.inc
    M tcg/mips/tcg-target-con-set.h
    M tcg/mips/tcg-target-con-str.h
    M tcg/mips/tcg-target.c.inc
    M tcg/mips/tcg-target.h
    M tcg/ppc/tcg-target-con-set.h
    M tcg/ppc/tcg-target-con-str.h
    M tcg/ppc/tcg-target.c.inc
    M tcg/riscv/tcg-target-con-set.h
    M tcg/riscv/tcg-target-con-str.h
    M tcg/riscv/tcg-target.c.inc
    M tcg/s390x/tcg-target-con-set.h
    M tcg/s390x/tcg-target-con-str.h
    M tcg/s390x/tcg-target.c.inc
    M tcg/tcg.c
    M trace/control-target.c

  Log Message:
  -----------
  Merge tag 'pull-tcg-20230511-2' of https://gitlab.com/rth7680/qemu into 
staging

target/m68k: Fix gen_load_fp regression
accel/tcg: Ensure fairness with icount
disas: Move disas.c into the target-independent source sets
tcg: Use common routines for calling slow path helpers
tcg/*: Cleanups to qemu_ld/st constraints
tcg: Remove TARGET_ALIGNED_ONLY
accel/tcg: Reorg system mode load/store helpers

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# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" 
[ultimate]

* tag 'pull-tcg-20230511-2' of https://gitlab.com/rth7680/qemu: (53 commits)
  target/loongarch: Do not include tcg-ldst.h
  accel/tcg: Reorg system mode store helpers
  accel/tcg: Reorg system mode load helpers
  accel/tcg: Introduce tlb_read_idx
  accel/tcg: Add cpu_in_serial_context
  tcg: Remove TARGET_ALIGNED_ONLY
  target/sh4: Remove TARGET_ALIGNED_ONLY
  target/sh4: Use MO_ALIGN where required
  target/nios2: Remove TARGET_ALIGNED_ONLY
  target/mips: Remove TARGET_ALIGNED_ONLY
  target/mips: Use MO_ALIGN instead of 0
  target/mips: Add missing default_tcg_memop_mask
  target/mips: Add MO_ALIGN to gen_llwp, gen_scwp
  tcg/s390x: Simplify constraints on qemu_ld/st
  tcg/s390x: Use ALGFR in constructing softmmu host address
  tcg/riscv: Simplify constraints on qemu_ld/st
  tcg/ppc: Remove unused constraint J
  tcg/ppc: Remove unused constraints A, B, C, D
  tcg/ppc: Adjust constraints on qemu_ld/st
  tcg/ppc: Reorg tcg_out_tlb_read
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Compare: https://github.com/qemu/qemu/compare/fff86d48a2cd...278238505d28
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